PCI Express® (PCIe®) technology is the most important high-speed serial bus in servers. Due to its high bandwidth and low latency characteristics, PCI Express architecture is widely used in various server interconnect scenarios. At the same time, with the rapid development of heterogeneous computing, the data throughput requirements in the server system are becoming higher and higher. Two years after the release of the PCIe 4.0 specification, the PCIe 5.0 specification was officially released in May 2019. PCIe 5.0 technology still uses the same 128b / 130b coding scheme, and the symbol rate increased from 16 GT/s to 32 GT/s. In keeping with tradition, the PCIe 5.0 specification is backwards compatible with lower-speed PCIe generations.
PCI Express® 5.0 Architecture Channel Insertion Loss Budget
Simulating with Retimers for PCIe 5.0
The design solution space for high-speed serial links is becoming increasingly complex with increasing data rates, diverse channel topologies, and tuning parameters for active components. PCI Express® 5.0, at 32 GT/s, is a particularly relevant example of an application whose design solution space can be a daunting problem to tackle, given the performance-cost requirements of its end equipment. This paper is intended to help system designers navigate these design challenges by providing a how-to guide for defining, executing, and analyzing system-level simulations, including PCIe 5.0 Root Complex (RC), Retimer, and End Point (EP).
Aries Smart Retimer Introduction
Astera Labs Chief Business Officer, Sanjay Gajendra, and Head of Engineering Operations, Nate Unger, introduce the Aries Smart Retimer portfolio for PCIe® 4.0 and 5.0 applications.
Aries PCIe Smart Retimer — a low-power, low-space, and low-latency solution, supports a wide topology of applications, along with bifurcation capabilities. Advanced features, such as built-in diagnostics and fleet management capability, enable easy system bring-up and large cloud deployment.
The Aries Smart Retimer portfolio doubles the reach and achieves plug-and-play interoperability with CPUs and endpoints while meeting PCI-SIG® compliance.
PCIe Retimer Overview – Presented by Astera Labs for PCI-SIG
In this video, Casey Morrison gives a quick tutorial on PCIe® Retimers – What do they do? When to use them? What key features to look for? PCI-SIG compliance requirements, etc.
Signal-integrity challenges will be significant in PCIe Gen 4.0 and Gen 5.0 due to increased data rates. A PCIe Retimer is a cost-optimized option to provide more margins and enable a robust link. Compliance tests meeting electrical and protocol specifications, latency, small total footprint, power consumption, bifurcation capacity, in-band and side-band diagnostics are key features system designers should look for in Retimers.
PCI Express Retimers vs. Redrivers: An Eye-Popping Difference
Retimers and Redrivers have enabled longer physical channels in servers and storage systems since Peripheral Component Interface Express (PCIe®) 3.0 was first introduced almost 10 years ago. Now that PCIe 4.0 is ramping up and PCIe 5.0 is just around the corner, how do these reach extension tools stack up in the face of new challenges in high-speed connectivity?
This article explains the differences between Retimers and Redrivers in IC block diagram, capabilities and use cases.
The impact of Bit Errors in PCI Express Links: The Painful Realities of Low-Probability Events
Retimers and Redrivers have enabled longer physical channels in servers and storage systems since Peripheral Component Interface Express (PCIe®) 3.0 was first introduced almost 10 years ago. Now that PCIe 4.0 is ramping up and PCIe 5.0 is just around the corner, how do these reach extension tools stack up in the face of new challenges in high-speed connectivity?
This article explains the differences between Retimers and Redrivers in IC block diagram, capabilities and use cases.