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There are generally three ways to approach this: 

1. Channel Loss Budget Analysis
2. Simulate channel s-parameter in the Statistical Eye Analysis Simulator (SeaSim) tool to determine if post-equalized eye height (EH) and eye width (EW) meet the minimum eye opening requirements: ≥6 mV EH and ≥3.13 ps EW at Bit Error Ratio (BER) ≤ 10-6. Refer to PCIe Base Specfication Section 8.5.1.
3. Consider your cost threshold for system upgrades 

A redriver amplifies a signal, whereas a Retimer retransmits a fresh copy of the signal.

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For PCIe 6.x, 36 dB at 16 GHz pre–channel and 36 dB at 16 GHz post– channel. Based on the PCIe Base Specification, the maximum total insertion loss with one retimer from Root Complex to End Point is 32 dB at 16 GHz, die to die.

There is no need to fine tune a Retimer EQ setting as it participates in Link Equalization with Root Complex and End Points and automatically fine tunes the receiver EQ.

The maximum number to cascade Retimers in a link is 2, which is defined in PCIe specification.

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There are no “special” considerations. During Equalization Phase 2, the Retimer’s upstream pseudo port (USPP) and the Endpoint will simultaneously train their receivers, and they have a total 64 ms at 64 GT/s speed (32 ms at lower speeds) to complete their Phase 2 training. During Equalization Phase 3, the same will happen with the downstream pseudo port (DSPP) and the root complex, and likewise a total of 64 ms at 64 GT/s speed (32 ms at lower speeds) is provided to complete Phase 3 training. The timeouts are the same regardless of whether a Retimer is present or not.

Not quite, each port of a packet switch has a full PCIe protocol stack:
Physical Layer, Data Link Layer, and Transaction Layer.

A packet switch has at least one root port and at least one non-root port.

A Retimer, by contrast, has an upstream-facing Physical Layer and a downstream-facing Physical Layer but no Data Link or Transaction Layer.

As such, a Retimer’s ports are considered pseudo ports because a Retimer does not have — nor does it need — these higher-logic layers, the latency through a Retimer is much smaller compared to the latency through a packet switch.

The only notable differences are: 

• As with all PCIe 6.x transmitters, the Retimer’s transmitters must support 64 GT/s precoding when requested by the link partner. 
• As with all PCIe 6.x receivers, the Retimer’s receivers must support Lane Margining in both time and voltage. 

A Retimer is required to have the same link width on its upstream-facing port and on its downstream-facing port. In other words, the link widths must match. A Retimer must also support down-configured link widths, but the width must always be the same on both ports.

Redrivers are not defined or specified within the PCIe Base Specification, so there are no formal guidelines for using a Redriver versus using a Retimer.

A Retimer’s transmitters and receivers, on both pseudo ports, must meet the PCIe Base Specifications. This means that a Retimer can support the full channel budget (nominally 36 dB at 16 GHz) on both sides — before and after the Retimer. Calculating the insertion loss (IL) budget should be done separately for each side of the Retimer, and channel compliance should be performed for each side as well, just as you would do for a Retimer-less Root-Complex-to-Endpoint link.

Redrivers and Retimers are active components which impact the data stream: their package imposes signal attenuation, their active circuits apply boost, and (in the case of Retimers) clock and data recovery. As such, there is no way to truly disable these components and still have data pass through. When disabled, no data will pass through a Redriver or Retimer.

1. Determine if a Retimer is needed based on different PCB materials
2. Define a simulation space, and identify worst-case conditions (temperature, humidity, impedance, etc.), minimum set of parameters (e.g., Transmitter Presets)
3. Define the evaluation criteria, such as minimum eye height/width
4. Execute and analyze results

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Bit error rate (BER) is the ultimate gauge of link performance, but an accurate measure of BER is not possible in relatively short, multi-million-bit simulations.

Instead, this analysis suggests the following pass/fail criteria, which consist of two rules:

1. 1. A link must meet the receiver’s eye height (EH) and eye width (EW) requirements
   2. A link must meet criteria 1 for at least half of Tx Preset settings (≥5 out of 10)

• Criteria 1 establishes that the there is a viable set of settings, which results in the desired BER. The specific EH and EW required by the receiver is implementation-dependent.
• Criteria 2 ensures that the link has adequate margin and is not overly sensitive to the Tx Preset setting.

View Signal Integrity Challenges for PCIe 5.0 OCP Topologies Video >

Use IBIS model and time domain simulations.

There are two primary applications for Aries Smart Cable Modules.

The first is to enable higher bandwidth and lower latency GPU-to-GPU and GPU-to-Switch multi-rack connectivity for larger AI clusters. As larger clusters of GPUs are deployed to address the increasing bandwidth and memory demands of AI workloads, AI infrastructure must scale GPU clusters across racks as server racks can only accommodate a certain number of GPUs due to power and thermal management constraints. Aries SCMs extend high-bandwidth PCIe 5.0. and CXL signal reach at 128 GB/s up to 7 meters to enable larger GPU clusters in a multi-rack architecture. Also, Aries SCMs improve cable routing, serviceability, and air flow with thin copper cables to maintain existing rack power and thermal density.

The second is to enable extended CXL reach for low-latency memory fabric connectivity in high-capacity in-memory compute architectures. Hyperscalers are deploying CXL memory expansion and pooling solutions to achieve higher application performance and the distances between the processor and expanded memory resources are increasing. Aries SCMs extend high-bandwidth PCIe 5.0 and CXL signal reach at 128 GB/s up to 7 meters to enable low-latency memory fabrics for scalable cloud infrastructure.

General-purpose AECs lack advanced cable and fleet management features essential managing data center infrastructure, while AECs with Aries SCMs offer system-wide visibility and management features through COSMOS that enable enhanced security, quick debug, and flexible firmware upgrade. 

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There are two key differences between Ethernet AECs vs PCIe AECs:

1. Protocol complexity: PCIe’s backwards compatibility and link training requirements make AECs more complex for PCIe compared to Ethernet.
2. Interoperability: The variety of device types and ecosystem players is significantly more for PCIe compared to Ethernet

Aries SCMs extend high-bandwidth PCIe 5.0 signal reach at 128 GB/s up to 7 meters to enable larger GPU clusters in a multi-rack architecture and low-latency memory fabrics for scalable cloud infrastructure.

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Aries SCMs are an offering within Astera Labs’ COSMOS suite enables system baseboard/system management controllers (BMCs/SMCs) to utilize an array of customizable diagnostics and telemetry features to enable continuous monitoring of critical server-to-JBOG, JBOG-to-JBOG, and Switch-to-JBOG links. Parameters such as eye opening, equalization levels, junction temperature, and more are monitored, and interrupts to the host can be enabled whenever configurable limits are crossed. A full set of self-test features—host-side and line-side loopback, pseudo-random bit sequence (PRBS) generation and checking, etc.—enable rapid troubleshooting to minimize link down time and accelerate fault isolation.

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Aries Smart Cable Modules support the multiple form factors and cable configurations for diverse AI topologies.

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Aries Smart Cable Modules can support a variety of gauges up to 7 meters.

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“RAS” is the ability of the system to provide resilience starting from the underlying hardware all the way to the application software through three components collectively referred to as “RAS” features: ​

1. Reliability: the ability of the system to detect and correct faults​
2. Availability: how the system guarantees uninterrupted operation with minimal degradation
3. Serviceability: the ability of the system to proactively diagnose, repair, upgrade or replace components at scale​