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Careers

Astera Labs is always looking for talented, knowledgeable, and dedicated individuals who are interested in becoming a member of our team. Positions within Astera Labs include:

Digital Design Engineer

Responsible for micro-architecture and implementation of the front-end design, including RTL, synthesis, IP integration, and block-level verification. Interface with PD team for timing closure. Familiar with UVM flow and DFT architecture. Excellent team player with solid communication skills.

  • Experience: BSEE/MSEE; 5+ years, 8+ years for senior/lead positions

  • Keywords: Embedded processors, PCIe, Ethernet networking, DDR, Cadence/Synopsys, FPGA design flows and tools, UVM verification flow

 

Design Verification Engineer

Responsible for all aspects of UVM based verification flow for complex connectivity semiconductor products. The candidate must have experience using Verification IPs from 3rd party vendors and should have good knowledge of communication protocols such as PCIe, Ethernet, NVMe and DDR.

  • Experience: BSEE/MSEE; 5+ years, 8+ years for senior/lead positions

  • Keywords: Embedded processors, PCIe, Ethernet networking, DDR, Cadence/Synopsys VIP tools, FPGA design flows and tools, UVM verification flow

 

Field Applications and Systems Engineer

Responsible for identifying and understanding customer needs and opportunities, proposing Astera Labs solutions which provide clear value to the customer, and providing hands-on design-in support. You will drive innovation by gathering customer requirements, defining new products, and working with some of the brightest engineers in the industry.

  • Experience: BSEE/MSEE; 5+ years, 8+ years for senior/lead positions

  • Keywords: FAE, Applications, Schematic, Layout, Product Definition, Python

 

Validation Engineer

Responsible for developing and performing post-silicon validation tests using advanced high-speed test equipment and scalable automation platforms. The validation team holds customers’ system requirements in the highest regard and is solely responsible for certifying a product’s conformance to this high bar. Validation is a data-driven and spec-driven function with heavy automation to support this approach.

  • Experience: BSEE/MSEE; 5+ years, 8+ years for senior/lead positions

  • Keywords: Python, Design-of-Experiments, Validation, BERT, Scope, Python (again)

 
 

Firmware Engineer

Responsible for software architecture and development of firmware/system software for network and storage controller management protocols. Extensive knowledge of C, Embedded software, Ethernet networking. Excellent team player with solid communication skills.

  • Experience: BSEE/MSEE; 5+ years, 8+ years for senior/lead positions

  • Keywords: TCP/IP, RTOS, JTAG, ARM, Python

Test Engineer

Responsible for developing and overseeing SoC test strategy, interacting with manufacturing partners, writing and implementing ATE programs, and owning the product from initial samples all the way through high-volume production ramp.

  • Experience: BSEE/MSEE; 5+ years, 8+ years for senior/lead positions

  • Keywords: Test, Scan, MEMBIST, ATE, Probe

 

Physical Design Engineer

Responsible for all implementation phases from netlist to GDSII. Experience with Fin-FET processes required. Hands-on experience with place and route, timing closure, physical verification and tapeout checks is a must. Deep knowledge of industry standard tools. Knowledge of DFT architecture and scan insertion preferred. Must have solid communication skills. 

  • Experience: MSEE/BSEE; 8+ years 

  • Keywords: TSMC, Fin-FET, PrimeTime, ICC, TetraMAX, Innovus, Tempus, Modus, etc.