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Careers

Astera Labs is always looking for talented, knowledgeable, and dedicated individuals who are interested in becoming a member of our team. Positions within Astera Labs include:

Software Engineer

Responsible for architecture and implementation of low-level software for in-fleet diagnostics, system qualification, and continuous monitoring for server, storage, and networking equipment or subsystems. Demonstrated leadership and communication skills. Working knowledge of BIOS functions as it relates to BMC.

  • Experience: BSCS/MSCS; 5+ years developing Python Packages and C Libraries

  • Keywords: Python, C, GitHub, BMC

 

Architect

Responsible for overall chip architecture, including IP integration, working with IP vendors for embedded processors, high bandwidth IO and memory interconnect with multiple clock domains. Demonstrated leadership and communication skills.

  • Experience: MSEE/PhD; 10+ years developing communication and/or processor SoCs

  • Keywords: Accelerators, PCIe, NVMe, Ethernet networking 

 

Digital Design Engineer

Responsible for micro-architecture and implementation of the front-end design, including RTL, synthesis, IP integration, and block-level verification. Interface with PD team for timing closure. Familiar with UVM flow and DFT architecture. Excellent team player with solid communication skills.

  • Experience: BSEE/MSEE; 5+ years, 8+ years for senior/lead positions

  • Keywords: Embedded processors, PCIe, Ethernet networking, DDR, Cadence/Synopsys, FPGA design flows and tools, UVM verification flow.  

 

Analog Mixed Signal Design Engineer

Responsible for the development of Analog front end, DSP equalization, and Clock-Data-Recovery circuits for 10s of GHz to address high bandwidth IO and memory interconnects in Data Center applications. Excellent team player with solid communication skills with recent experience with advanced Fin-FET technologies.

  • Experience: MSEE/PhD; 5+ years, 8+ years for senior/lead positions

  • Keywords: PCIe, Ethernet networking, DDR, AFE, CTLE, DFE, VGA, ADC, DAC, CDR, PLL, VCO   

 

Design Verification Engineer

Responsible for all aspects of UVM based verification flow for complex connectivity semiconductor products. The candidate must have experience using Verification IPs from 3rd party vendors and should have good knowledge of communication protocols such as PCIe, Ethernet, NVMe and DDR.

  • Experience: BSEE/MSEE; 5+ years, 8+ years for senior/lead positions

  • Keywords: Embedded processors, PCIe, Ethernet networking, DDR, Cadence/Synopsys VIP tools, FPGA design flows and tools, UVM verification flow.  

 

Physical Design Engineer

Responsible for all implementation phases from netlist to GDSII. Experience with Fin-FET processes required. Hands-on experience with place and route, timing closure, physical verification and tapeout checks is a must. Deep knowledge of industry standard tools. Knowledge of DFT architecture and scan insertion preferred. Must have solid communication skills. 

  • Experience: MSEE/BSEE; 8+ years 

  • Keywords: TSMC, Fin-FET, PrimeTime, ICC, TetraMAX, Innovus, Tempus, Modus, etc.

 

Firmware Engineer

Responsible for software architecture and development of firmware/system software for network and storage controller management protocols. Extensive knowledge of C, Embedded software, Ethernet networking. Excellent team player with solid communication skills.

  • Experience: BSEE/MSEE; 5+ years, 8+ years for senior/lead positions

  • Keywords: TCP/IP, RTOS, JTAG, ARM, Python.