COVID-19 Impact
The global pandemic means we can't gather together in person.
Check back here for details on virtual events as they are scheduled. And in the meantime, check out content from past events below.
End-to-End System-Level Simulations with Retimers for PCIe® 5.0 & CXL™: A How-To Guide
This presentation provides a how-to guide for analyzing and optimizing PCI Express® 5.0 interconnects with Retimers using an EDA simulation flow and system design best practices. Common PCIe system topology examples are provided, and a start-to-finish analysis methodology is proposed including placement, material selection, and simulation.
By Casey Morrison, Astera Labs
