October 27 – 28, 2021
Astera Labs will showcase how Aries Smart Retimers enable robust CXL and PCIe 5.0 connectivity between a CPU and multiple endpoints at the Industry Enabling Zone. Visit our virtual booth and chat with Astera Labs' experts about new purpose-built connectivity solutions that unlock your system performance.
End-to-End System-Level Simulations with Retimers for PCIe® 5.0 & CXL™: A How-To Guide
This presentation provides a how-to guide for analyzing and optimizing PCI Express® 5.0 interconnects with Retimers using an EDA simulation flow and system design best practices. Common PCIe system topology examples are provided, and a start-to-finish analysis methodology is proposed including placement, material selection, and simulation.
By Casey Morrison, Astera Labs