The explosion of data and rapid growth in specialized workloads — like artificial intelligence (AI) and machine learning — have given rise to heterogeneous computing and composable disaggregation topologies. Purpose-built connectivity solutions from Astera Labs address the performance bottlenecks in these data-centric systems.
Unlock Low-Latency Connectivity in Complex System Topologies
Astera Labs Makes it Happen
Astera Labs’ solutions are purpose-built to tackle bandwidth, capacity, and performance bottlenecks in data-centric systems. Our system-aware semiconductor products, boards and services enable robust CXL™ 1.1/2.0, PCIe® 4.0/5.0 connectivity, providing deep diagnostics and fleet management capabilities to both system designers and cloud service providers.
Server Connectivity Backbone
High-bandwidth, low-latency interconnects for compute, storage and accelerator resources
GPUs & AI Accelerators
Robust PCIe 4.0, PCIe 5.0, and CXL connectivity between GPUs, AIPs and FPGAs in JBoG or AI-box applications
Networking
Copper-based 400G/800G Ethernet rack connectivity between server-to-switch and switch-to-switch applications
Products & Services
Purpose-built ICs
Purpose-built silicon ICs to address connectivity bottlenecks throughout the data center
What Our Customers & Partners Say
“… Astera Labs has been a contributor to the advancement of our specifications with its expertise of PCIe retimer technology… It is great to see Aries Smart Retimers broadly available to system developers, which will enable rapid PCIe 4.0 technology and PCIe 5.0 technology ecosystem expansion.”
Al Yanes, Chairman and President
PCI-SIG
“As an early CXL Consortium member, Astera Labs contributed its connectivity expertise to the advancement of the CXL standard.”
Barry McAuliffe, President
CXL Consortium
“Intel is… leading the transition with its support for the new PCIe 5.0 specification and the announcement of Compute Express Link (CXL) technology. We are excited that Astera Labs has entered the ecosystem to develop purpose-built connectivity solutions to enable seamless adoption of these technologies.”
Amber Huffman, Intel Fellow
Intel
“… we’re excited to take part in Astera Labs’ Cloud-Scale Interop Lab to support Aries Smart Retimers for enterprise PCIe 4.0 system designers.”
Richard New, Vice President of Research
Western Digital
“Astera Labs’ innovative technology is in alignment with Intel’s strategy to accelerate processing for CPUs and purpose-built accelerators for the next generation of data-centric platforms that support emerging applications… We’re excited to be strategic investors and technology partners with Astera Labs to enable these emerging ecosystems.”
Mark Rostick, Vice President and Senior Managing Director
Intel Capital
“With a focus on cutting-edge technology and a long list of early customer adopters, [Astera Labs] is a perfect fit for our technology portfolio.”
Stefan Dyckerhoff, Managing Director
Sutter Hill Ventures
“Enterprise-class PCIe 4.0 and 5.0 retimer solutions that interoperate with Intel platforms, such as Astera Labs’ Aries Smart Retimers, are instrumental to the enablement of high-performance standard PCIe 5.0 interconnect across the entire ecosystem.”
Michael Hall, Director of Technology and Ecosystem Enabling
Intel
“The Cloud-Scale Interop Lab from Astera Labs helps ensure seamless interoperability within the latest PCIe 4.0 systems and verifies that the resulting connection can handle the rigors of enterprise operation.”
Hangu Sohn, Vice President of NAND Memory Planning
Samsung Electronics
“I believe Astera Labs’ latest CXL and PCIe connectivity solutions are fundamental to realizing the full potential of Artificial Intelligence in the Cloud.”
Avigdor Willenz
Astera Labs’ Founding Investor
“We are pleased to collaborate with Astera Labs… to deliver Aries Smart Retimers to market… quickly satisfying the massive customer demand for their cloud-optimized connectivity solutions.”
Bradford Paulsen, Senior Vice President of Business Management
TSMC North America
“Intel is collaborating with ecosystem leaders like Astera Labs to significantly reduce PCIe and CXL interconnect latency on upcoming Intel Xeon Scalable platform code-named ‘Sapphire Rapids’ and additional platforms.”
Zane Ball, Corporate VP and General Manager Datacenter Engineering and Architecture
Intel
“We’re pleased to continue our collaboration with Astera Labs to support accelerated scale with the delivery of their PCIe solutions today and emerging CXL solutions tomorrow.”
Zane Ball, Corporate VP & GM, Data Platforms Engineering & Architecture
Intel
“Astera Labs is primed and ready to grow rapidly, as it delivers solutions that enable the expanding AI ecosystem… Its mission to innovate exponentially, rather than incrementally, aligns with my own approach of building companies that create the technologies that change our world.”
Avigdor Willenz
“QCT is leading the way to solve… next-generation datacenter design and operation challenges, and we are excited to partner with Astera Labs on purpose-built PCIe Smart Retimer solutions.”
Mike Yang, President
Quanta Cloud Technology
Data Center Resource Disaggregation Drives Need for Cost-Effective 400/800-GbE Interconnects
As new compute-intensive machine learning (ML) and artificial intelligence (AI) workloads drive servers to adopt faster PCI Express® 5.0 Links, lower-latency cache-coherent protocols like Compute Express Link™ (CXL™), and a dizzying array of memory, storage, AI processor (AIP), smart NIC, FPGA, and GPU elements, so too is heterogeneous computing pushing the need for blazing-fast networks to interconnect the resources.
PCI Express® 5.0 Architecture Channel Insertion Loss Budget
The upgrade from PCIe® 4.0 to PCIe 5.0 doubles the bandwidth from 16GT/s to 32GT/s but also suffers greater attenuation per unit distance, despite the PCIe 5.0 specification increasing the total insertion loss budget to 36dB. After deducting the loss budget for CPU package, AIC, and CEM connector, merely 16dB system board budget remains. Within the remaining budget, engineers need to consider safety margin for board loss variations due to temperature and humidity.
Simulating with Retimers for PCIe® 5.0
The design solution space for high-speed serial links is becoming increasingly complex with increasing data rates, diverse channel topologies, and tuning parameters for active components. PCI Express® (PCIe®) 5.0, at 32 GT/s, is a particularly relevant example of an application whose design solution space can be a daunting problem to tackle, given the performance-cost requirements of its end equipment. This paper is intended to help system designers navigate these design challenges by providing a how-to guide for defining, executing, and analyzing system-level simulations, including PCIe 5.0 Root Complex (RC), Retimer, and End Point (EP).