The explosion of data and rapid growth in specialized workloads — like artificial intelligence (AI) and machine learning — have given rise to heterogeneous computing and composable disaggregation topologies. Purpose-built connectivity solutions from Astera Labs address the performance bottlenecks in these data-centric systems.
Unlock Low-Latency Connectivity in Complex System Topologies
Astera Labs Makes it Happen
Astera Labs’ solutions are purpose-built to tackle bandwidth, capacity, and performance bottlenecks in data-centric systems. Our system-aware semiconductor products, boards and services enable robust CXL™ 1.1/2.0, PCIe® 4.0/5.0 connectivity, providing deep diagnostics and fleet management capabilities to both system designers and cloud service providers.
Server Connectivity Backbone
High-bandwidth, low-latency interconnects for compute, storage and accelerator resources
GPUs & AI Accelerators
Robust PCIe 4.0, PCIe 5.0, and CXL connectivity between GPUs, AIPs and FPGAs in JBoG or AI-box applications
Networking
Copper-based 400G/800G Ethernet rack connectivity between server-to-switch and switch-to-switch applications
Products & Services
Purpose-built ICs
Purpose-built silicon ICs to address connectivity bottlenecks throughout the data center
What Our Customers & Partners Say

Data Center Resource Disaggregation Drives Need for Cost-Effective 400/800-GbE Interconnects
As new compute-intensive machine learning (ML) and artificial intelligence (AI) workloads drive servers to adopt faster PCI Express® 5.0 Links, lower-latency cache-coherent protocols like Compute Express Link™ (CXL™), and a dizzying array of memory, storage, AI processor (AIP), smart NIC, FPGA, and GPU elements, so too is heterogeneous computing pushing the need for blazing-fast networks to interconnect the resources.

PCI Express® 5.0 Architecture Channel Insertion Loss Budget
The upgrade from PCIe® 4.0 to PCIe 5.0 doubles the bandwidth from 16GT/s to 32GT/s but also suffers greater attenuation per unit distance, despite the PCIe 5.0 specification increasing the total insertion loss budget to 36dB. After deducting the loss budget for CPU package, AIC, and CEM connector, merely 16dB system board budget remains. Within the remaining budget, engineers need to consider safety margin for board loss variations due to temperature and humidity.

Simulating with Retimers for PCIe® 5.0
The design solution space for high-speed serial links is becoming increasingly complex with increasing data rates, diverse channel topologies, and tuning parameters for active components. PCI Express® (PCIe®) 5.0, at 32 GT/s, is a particularly relevant example of an application whose design solution space can be a daunting problem to tackle, given the performance-cost requirements of its end equipment. This paper is intended to help system designers navigate these design challenges by providing a how-to guide for defining, executing, and analyzing system-level simulations, including PCIe 5.0 Root Complex (RC), Retimer, and End Point (EP).