Purpose-Built Connectivity Solutions for Intelligent Systems
The explosion of data and rapid growth in specialized workloads — like Artificial Intelligence (AI) and Machine Learning (ML) — have given rise to heterogeneous computing and composable disaggregation topologies. Purpose-built data and memory connectivity solutions from Astera Labs address the performance bottlenecks in these data-centric systems.
Unlock Low-Latency Connectivity in Complex System Topologies
Astera Labs Makes it Happen
Astera Labs’ solutions are purpose-built to tackle bandwidth, capacity, and performance bottlenecks in data-centric systems. Our system-aware semiconductor products, boards and services enable robust CXL™ 1.1/2.0, PCIe® 4.0/5.0, and 100G/Lane Ethernet connectivity, providing deep diagnostics and fleet management capabilities to both system designers and cloud service providers.
GPUs & AI Accelerators
Reliable PCIe 4.0, PCIe 5.0, and CXL connectivity for GPUs (JBoG), AIPs and FPGAs with maximum link up-time
Networking
Copper-based 100G/Lane Ethernet rack connectivity between server-to-switch and switch-to-switch applications
Products & Services
Purpose-built ICs
Purpose-built silicon ICs to address connectivity bottlenecks throughout the data center
What Our Customers & Partners Say
“CXL is designed to be an open standard interface to support composable memory infrastructure that can expand and share memory resources to bring greater efficiency to modern data centers.We’re excited to work closely with Astera Labs on the development of their Leo Memory Connectivity Platform to deliver interoperability and robust validation with AMD processors and accelerators.”
Raghu Nambiar, Corporate Vice President, Data Center Ecosystems and Solutions
AMD
“CXL provides a platform for a wealth of memory connectivity options and innovations in next-generation server architectures, which is essential for the industry to realize the tremendous potential of data-centric applications. Our continued collaboration with the CXL ecosystem providers, such as Astera Labs through their Leo Memory Connectivity Platform, will help enable customers to develop reliable, interoperable CXL memory expansion and pooling solutions.”
Zane Ball, Corporate VP and General Manager Datacenter Engineering and Architecture
Intel
“Astera Labs continues to be a valuable contributor to the CXL Consortium with its connectivity expertise and commitment to vendor-neutral interoperability. We’re excited to see Astera Labs deliver a solution to help enable a rapidly growing marketplace of CXL memory expansion and pooling products.”
Siamak Tavallaei, President
CXL Consortium
“QCT is leading the way to solve… next-generation datacenter design and operation challenges, and we are excited to partner with Astera Labs on purpose-built PCIe Smart Retimer solutions.”
Mike Yang, President
Quanta Cloud Technology
“We are pleased to collaborate with Astera Labs… to deliver Aries Smart Retimers to market… quickly satisfying the massive customer demand for their cloud-optimized connectivity solutions.”
Bradford Paulsen, Senior Vice President of Business Management
TSMC North America
“Solutions like Astera Labs’ Leo Memory Accelerator Platform are critical to enable tighter coupling between AMD processors, accelerators and memory expansion.”
Michael Hall, Director of Customer Compatibility
AMD
“… Astera Labs has been a contributor to the advancement of our specifications with its expertise of PCIe retimer technology… It is great to see Aries Smart Retimers broadly available to system developers, which will enable rapid PCIe 4.0 technology and PCIe 5.0 technology ecosystem expansion.”
Al Yanes, Chairman and President
PCI-SIG
“… we’re excited to take part in Astera Labs’ Cloud-Scale Interop Lab to support Aries Smart Retimers for enterprise PCIe 4.0 system designers.”
Richard New, Vice President of Research
Western Digital
“The Cloud-Scale Interop Lab from Astera Labs helps ensure seamless interoperability within the latest PCIe 4.0 systems and verifies that the resulting connection can handle the rigors of enterprise operation.”
Hangu Sohn, Vice President of NAND Memory Planning
Samsung Electronics
“We are very excited with the growth and expansion of Astera Labs and remain highly optimistic about the long-term potential of the company.”
Stefan Dyckerhoff, Managing Director
Sutter Hill Ventures
“Astera Labs’ innovative technology is in alignment with Intel’s strategy to accelerate processing for CPUs and purpose-built accelerators for the next generation of data-centric platforms that support emerging applications… We’re excited to be strategic investors and technology partners with Astera Labs to enable these emerging ecosystems.”
Mark Rostick, Vice President and Senior Managing Director
Intel Capital
“Astera Labs has done a tremendous job in developing a portfolio of multiple innovative products that address critical needs of heterogeneous computing and composable disaggregation infrastructure.”
Avigdor Willenz
Astera Labs’ Founding Investor
“Intel is… leading the transition with its support for the new PCIe 5.0 specification and the announcement of Compute Express Link (CXL) technology. We are excited that Astera Labs has entered the ecosystem to develop purpose-built connectivity solutions to enable seamless adoption of these technologies.”
Amber Huffman, Intel Fellow
Intel
“I believe Astera Labs’ latest CXL and PCIe connectivity solutions are fundamental to realizing the full potential of Artificial Intelligence in the Cloud.”
Avigdor Willenz
Astera Labs’ Founding Investor
"As a trusted technology service provider for cloud computing customers, Wistron prides itself on delivering high-quality product differentiation through genuine innovation. We are excited to partner with Astera Labs, whose PCIe Smart Retimers are purpose-built to enable robust cloud connectivity with a drop-in upgrade from PCIe 4.0 to 5.0 and an extensive list of innovative fleet management capabilities that our customers truly value.”
William Lin, President of Enterprise Business Group
Wistron
“The GSA congratulates Astera Labs on being nominated as a finalist for the 2021 ‘Start-Up to Watch’ award… demonstrating vision and innovative application of its technology for overcoming barriers to realizing the benefits of artificial intelligence and machine learning in the cloud.”
Jodi Shelton, Co-Founder and CEO
Global Semiconductor Alliance
“I want to thank Astera Labs for investing in the Toronto Region’s post-pandemic economic recovery, creating high-value jobs, and contributing to our globally recognized technology sector.”
John Tory, Mayor
City of Toronto
“Astera Labs’ Taurus Smart Cables™ play an important role in enabling intra rack connectivity based on active copper cables for the 800GbE interconnect ecosystem.”
Alan Weckel, Founder and Technology Analyst
650 Group
“Astera Labs’ Leo CXL Memory Accelerator Platform is an important enabler for the Intel ecosystem to implement a shared memory space between hosts and attached-devices.”
Jim Pappas, Director of Technology Initiatives
Intel
“Arm sees CXL as a significant driver in this space, and Astera Labs’ new platform will help to address these needs in cloud and edge computing data centers using Arm®-based technology.”
John DaCosta, Senior Director, Strategic Segments
Arm
Unlocking Cloud Server Performance with CXL
The increasing volume of data and complexity of models requires advancements in cloud server architecture to remove memory bottlenecks and unlock the performance for compute-intensive workloads, such as Artificial Intelligence and Machine Learning. Leo Memory Connectivity Platform for CXL 1.1 and 2.0 eliminates the memory bottlenecks inherent in today’s architectures and enables new heterogeneous infrastructure to increase performance and reduce costs for cloud-scale deployment.
Connectivity Is Key to Harnessing the Data Reshaping Our World
As our appetite for creating and consuming massive amounts of data continues to grow, so too will our need for increased cloud capacity to store and analyze this data. Additionally, the server connectivity backbone for data center infrastructure needs to evolve as complex AI and ML workloads become mainstream in the cloud.
Taurus Smart Cable Modules™: An Active + Smart Approach to 200/400/800GbE
Today’s data center networks are primarily serviced by 25G/lane Ethernet technology; however, these networks are quickly moving to 50G and 100G/lane to allow hyperscalers to add additional servers and switches to their Clos Network topologies and support data-intensive workloads such as AI and Machine Learning. This rapid growth in Ethernet port speed is causing a new set of challenges for design complexity and serviceability of hyperscale architectures.
Astera Labs unveils new Vancouver location to further expand its leadership in purpose-built connectivity solutions for AI & ML infrastructure
“We are in a tremendous growth phase in every aspect of our business and the new Astera Labs Vancouver location will be instrumental in driving our continued expansion as a company and as the industry leader in advanced data and memory connectivity,” said Sanjay Gajendra, chief business officer, Astera Labs. “We thank Mayor Mike Hurley… Read More »
Astera Labs to host Mayor of Burnaby at grand opening of new Vancouver design center and lab
Astera Labs welcomes the Mayor of Burnaby and the Burnaby Board of Trade President and CEO to celebrate the grand opening of its new state-of-the-art design center and lab in the Greater Vancouver Area.
Astera Labs Enters Pre-Production Phase of Leo Memory Connectivity Platform for CXL-Attached Memory Expansion and Pooling
“Our Leo Memory Connectivity Platform for CXL 1.1 and 2.0 is purpose-built to overcome processor memory bandwidth bottlenecks and capacity limitations in accelerated and intelligent infrastructure,” said Jitendra Mohan, CEO, Astera Labs. “Successful delivery of Leo Smart Memory Controllers, Leo-based hardware board solutions and comprehensive software tools to our partners and customers represents a significant… Read More »