Server Connectivity Backbone
High-bandwidth interconnects for compute, storage, and accelerator resources.
Rapid Deployment of PCIe 4.0/5.0
Rapid deployment of PCIe 4.0 & 5.0 technology for processors, workload accelerators, smart I/Os, FPGAs, and more.
Distributed Machine Learning
Provide GPUs and accelerators with reliable connectivity and maximum link up-time.
Seamless Transition to PCIe® 5.0 Technology in System Implementations
In this PCI-SIG® hosted technical webinar, Astera Labs’ engineers explore the changes between PCIe 4.0 and PCIe 5.0 specifications, including signal integrity and system design challenges, where the right balance must be found between PCB materials, connector types and the use of signal conditioning devices for practical compute topologies. Through an objective analysis, the goal is to provide the audience with a methodology to optimize signal and link integrity performance, present best practices for system board design to support PCIe 5.0 technology applications, and test for system level interoperation.
PCI Express® 5.0 Architecture Channel Insertion Loss Budget
The upgrade from PCIe 4.0 to PCIe 5.0 doubles the bandwidth from 16GT/s to 32GT/s but also suffers greater attenuation per unit distance, despite the PCIe 5.0 specification increasing the total insertion loss budget to 36dB. After deducting the loss budget for CPU package, AIC, and CEM connector, merely 16dB system board budget remains. Within the remaining budget, engineers need to consider safety margin for board loss variations due to temperature and humidity.
Signal Integrity Challenges for PCIe 5.0 OCP Topologies
Astera Labs explains the signal integrity challenges of PCIe 5.0 and the corresponding OCP system design challenges, where the right balance must be found between PCB materials, connector types, and the use of signal conditioning devices for practical compute topologies: CPU-to-AIC with one/two connectors, JBOG accelerator module baseboard, etc.