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Careers

Home » Careers

Careers at Astera Labs

Astera Labs is always looking for talented, knowledgeable, and dedicated individuals who are interested in becoming a member of our team. Positions within Astera Labs include:

Global Sales Operations Lead

(Locations: San Francisco Bay Area)

Responsible for Pre-sales, Post-sales, and Sales Management Support, to include RFQ/Quote management, Customer Forecast/Distribution Management, Order Fulfillment and other support activities to maximize the efficiency of the Sales & Operation Teams. You will work closely with the Sales, Factory Operations, and Field/Product Applications Engineering to continuously analyze current processes and adapt/implement new processes to drive efficiencies of scale across the Sales and Operations team.

  • Experience: Bachelor or above degree in Business Administration or Engineering; 3+ year professional experience
  • Keywords: CRM, sales management
Submit Resume

US Regional Sales Executive

(Locations: San Francisco Bay Area)

Responsible for identifying target customers, size of Astera Labs sales opportunities and outlining steps to effectively engage and develop relationships within key influencers in R&D, Procurement, Executive level GM/CTO. You will work closely with Field Sales Engineers (FAEs) and the sales management team to develop an account strategy to effectively engage with leading cloud service providers, server and networking OEMs to design in Astera Labs’ portfolio of connectivity products.

  • Experience: Bachelor’s degree, preferred engineering and MBA; 5+ years, 8+ years for senior/lead positions
  • Keywords: Sales, Business Development, Strategy Planning
Submit Resume

Customer Business Specialist

(Locations: Taipei)

Responsible for working with sales team to support entire sales cycle from project qualification to close. You will support the sales team to develop an account strategy to effectively engage with leading cloud service providers, server and networking ODM/OEMs to design in Astera Labs’ portfolio of connectivity products.

  • Experience: Bachelor in Business Administration or Engineering; 3+ professional experiences
  • Keywords: CRM, order fulfillment
Submit Resume

Head of Program Management

(Locations: San Francisco Bay Area)

Responsible for driving development teams to deliver on the project milestones with minimal supervision, from initial architecture through device production. You will work closely with upper management delivering results on high priority business and operational objectives.

  • Experience: BSEE; 8+ years
  • Keywords: Program Management, Scrum, Jira, SoC
Submit Resume

Product Applications Engineer

(Locations: San Francisco Bay Area)

Responsible for providing technical guidance to customers to overcome design challenges, generating collateral for existing and new products, and driving innovation by providing insightful feedback to other internal teams to continuously improve products and processes.

  • Experience: BSEE/MSEE; 3+ years
  • Keywords: PCIe, Ethernet networking, DDR, Cadence/Synopsys, IBIS-AMI
Submit Resume

Digital Design Engineer

Responsible for micro-architecture and implementation of the front-end design, including RTL, synthesis, IP integration, and block-level verification. Interface with PD team for timing closure. Familiar with UVM flow and DFT architecture. Excellent team player with solid communication skills.

  • Experience: BSEE/MSEE; 5+ years, 8+ years for senior/lead positions
  • Keywords: Embedded processors, PCIe, Ethernet networking, DDR, Cadence/Synopsys, FPGA design flows and tools, UVM verification flow.
Submit Resume

Design Verification Engineer

Responsible for all aspects of UVM based verification flow for complex connectivity semiconductor products. The candidate must have experience using Verification IPs from 3rd party vendors and should have good knowledge of communication protocols such as PCIe, Ethernet, NVMe and DDR.

  • Experience: BSEE/MSEE; 5+ years, 8+ years for senior/lead positions
  • Keywords: Embedded processors, PCIe, Ethernet networking, DDR, Cadence/Synopsys VIP tools, FPGA design flows and tools, UVM verification flow.
Submit Resume

Systems Engineer

(Location: Taipei or Shanghai)

Responsible for working with next-generation server board platforms to perform interoperability testing with customer’s PCIe Gen-4 and Gen-5 cards. You will become an expert on Astera Labs products and lead interoperability testing in Asia and work closely with the US engineering team. You will need to have a deep understanding of the PCIe LTSSM and demonstrated ability to learn SoC Architectures at a functional block level.

  • Experience: BSEE/MSEE; 5+ years, 8+ years for senior/lead positions
  • Keywords: LTSSM, Applications, Schematic, Layout, Product Definition, Python
Submit Resume

Asia Field Applications Engineers

(Locations: Beijing, Shanghai, Taipei)

Responsible for identifying and understanding customer needs and opportunities, proposing Astera Labs solutions which provide clear value to the customer, and providing hands-on design-in support. You will drive innovation by gathering customer requirements, defining new products, and working with some of the brightest engineers in the industry.

  • Experience: BSEE/MSEE; 5+ years, 8+ years for senior/lead positions
  • Keywords: FAE, Applications, Schematic, Layout, Product Definition, Python
Submit Resume

US Regional Field Applications Engineer

(Locations: San Francisco Bay Area)

Responsible for identifying and understanding customer needs and opportunities, proposing Astera Labs solutions which provide clear value to the customer, and providing hands-on design-in support. You will drive innovation by gathering customer requirements, defining new products, and working with some of the brightest engineers in the industry.

  • Experience: BSEE/MSEE; 5+ years, 8+ years for senior/lead positions
  • Keywords: FAE, Applications, Schematic, Layout, Product Definition, Python
Submit Resume

Asia Regional Sales Executives

(Locations: Beijing, Shanghai, Taipei)

Responsible for identifying target customers, size of Astera Labs sales opportunities and outlining steps to effectively engage and develop relationships within key influencers in R&D, Procurement, Executive level GM/CTO.  You will work closely with Field Sales Engineers (FAEs) and the sales management team to develop an account strategy to effectively engage with leading cloud service providers, server and networking OEMs to design in Astera Labs’ portfolio of connectivity products.

  • Experience: Bachelor’s degree, preferred engineering and MBA; 5+ years, 8+ years for senior/lead positions
  • Keywords: Sales, Business Development, Strategy Planning
Submit Resume

Validation Engineer

Responsible for developing and performing post-silicon validation tests using advanced high-speed test equipment and scalable automation platforms. The validation team holds customers’ system requirements in the highest regard and is solely responsible for certifying a product’s conformance to this high bar. Validation is a data-driven and spec-driven function with heavy automation to support this approach.

  • Experience: BSEE/MSEE; 5+ years, 8+ years for senior/lead positions
  • Keywords: Python, Design-of-Experiments, Validation, BERT, Scope, Python (again)
Submit Resume

Firmware Engineer

Responsible for software architecture and development of firmware/system software for network and storage controller management protocols. Extensive knowledge of C, Embedded software, Ethernet networking. Excellent team player with solid communication skills.

  • Experience: BSEE/MSEE; 5+ years, 8+ years for senior/lead positions
  • Keywords: TCP/IP, RTOS, JTAG, ARM, Python.
Submit Resume

Test Engineer

Responsible for developing and overseeing SoC test strategy, interacting with manufacturing partners, writing and implementing ATE programs, and owning the product from initial samples all the way through high-volume production ramp.

  • Experience: BSEE/MSEE; 5+ years, 8+ years for senior/lead positions
  • Keywords: Test, Scan, MEMBIST, ATE, Probe
Submit Resume

Software Engineer

Responsible for architecture and implementation of low-level software for in-fleet diagnostics, system qualification, and continuous monitoring for server, storage, and networking equipment or subsystems. Demonstrated leadership and communication skills. Working knowledge of BIOS functions as it relates to BMC.

  • Experience: BSCS/MSCS; 5+ years developing Python Packages and C Libraries
  • Keywords: Python, C, GitHub, BMC
Submit Resume

Architect

Responsible for overall chip architecture, including IP integration, working with IP vendors for embedded processors, high bandwidth IO and memory interconnect with multiple clock domains. Demonstrated leadership and communication skills.

  • Experience: MSEE/PhD; 10+ years developing communication and/or processor SoCs
  • Keywords: Accelerators, PCIe, NVMe, Ethernet networking
Submit Resume

Analog Mixed Signal Design Engineer

Responsible for the development of Analog front end, DSP equalization, and Clock-Data-Recovery circuits for 10s of GHz to address high bandwidth IO and memory interconnects in Data Center applications. Excellent team player with solid communication skills with recent experience with advanced Fin-FET technologies.

  • Experience: MSEE/PhD; 5+ years, 8+ years for senior/lead positions
  • Keywords: PCIe, Ethernet networking, DDR, AFE, CTLE, DFE, VGA, ADC, DAC, CDR, PLL, VCO
Submit Resume

Physical Design Engineer

Responsible for all implementation phases from netlist to GDSII. Experience with Fin-FET processes required. Hands-on experience with place and route, timing closure, physical verification and tapeout checks is a must. Deep knowledge of industry standard tools. Knowledge of DFT architecture and scan insertion preferred. Must have solid communication skills.

  • Experience: MSEE/BSEE; 8+ years
  • Keywords: TSMC, Fin-FET, PrimeTime, ICC, TetraMAX, Innovus, Tempus, Modus, etc.
Submit Resume
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