Are you ready to make an immediate, lasting impact at a fast-paced, award-winning startup focused on developing game-changing connectivity solutions for data centers?
Join us to build great products, drive bleeding-edge technology, partner with industry-leading companies, and work with a dedicated, passionate, and collaborative team of engineers who are innovating exponentially to remove performance bottlenecks in compute intensive workloads such as AI and machine learning.
(Locations: Shanghai and Taipei)
Responsible for customer quality management to the world’s leading cloud service providers, server and network OEMs. In this role, you will need to apply your quality experience towards customer returns, root cause.
- Experience: BSEE, preferred master's in engineering
- Keywords: Quality, Failure Analysis
(Locations: San Francisco Bay Area, Pacific Northwest, Texas)
Responsible for identifying target customers, size of Astera Labs sales opportunities and outlining steps to effectively engage and develop relationships within key influencers in R&D, Procurement, Executive level GM/CTO. You will work closely with Field Sales Engineers (FAEs) and the sales management team to develop an account strategy to effectively engage with leading cloud service providers, server and networking OEMs to design in Astera Labs’ portfolio of connectivity products.
- Experience: Bachelor’s degree, preferred engineering and MBA; 5+ years, 8+ years for senior/lead positions
- Keywords: Sales, Business Development, Strategy Planning
(Locations: Taipei)
Responsible for working with sales team to support entire sales cycle from project qualification to close. You will support the sales team to develop an account strategy to effectively engage with leading cloud service providers, server and networking ODM/OEMs to design in Astera Labs’ portfolio of connectivity products.
- Experience: Bachelor in Business Administration or Engineering; 3+ professional experiences
- Keywords: CRM, order fulfillment
(Locations: San Francisco Bay Area)
Responsible for driving development teams to deliver on the project milestones with minimal supervision, from initial architecture through device production. You will work closely with upper management delivering results on high priority business and operational objectives.
- Experience: BSEE; 8+ years
- Keywords: Program Management, Scrum, Jira, SoC
(Locations: San Francisco Bay Area)
Responsible for providing technical guidance to customers to overcome design challenges, generating collateral for existing and new products, and driving innovation by providing insightful feedback to other internal teams to continuously improve products and processes.
- Experience: BSEE/MSEE; 3+ years
- Keywords: PCIe, Ethernet networking, DDR, Cadence/Synopsys, IBIS-AMI
Responsible for micro-architecture and implementation of the front-end design, including RTL, synthesis, IP integration, and block-level verification. Interface with PD team for timing closure. Familiar with UVM flow and DFT architecture. Excellent team player with solid communication skills.
- Experience: BSEE/MSEE; 5+ years, 8+ years for senior/lead positions
- Keywords: Embedded processors, PCIe, Ethernet networking, DDR, Cadence/Synopsys, FPGA design flows and tools, UVM verification flow.
Responsible for all aspects of UVM based verification flow for complex connectivity semiconductor products. The candidate must have experience using Verification IPs from 3rd party vendors and should have good knowledge of communication protocols such as PCIe, Ethernet, NVMe and DDR.
- Experience: BSEE/MSEE; 5+ years, 8+ years for senior/lead positions
- Keywords: Embedded processors, PCIe, Ethernet networking, DDR, Cadence/Synopsys VIP tools, FPGA design flows and tools, UVM verification flow.
(Location: Taipei or Shanghai)
Responsible for working with next-generation server board platforms to perform interoperability testing with customer’s PCIe Gen-4 and Gen-5 cards. You will become an expert on Astera Labs products and lead interoperability testing in Asia and work closely with the US engineering team. You will need to have a deep understanding of the PCIe LTSSM and demonstrated ability to learn SoC Architectures at a functional block level.
- Experience: BSEE/MSEE; 5+ years, 8+ years for senior/lead positions
- Keywords: LTSSM, Applications, Schematic, Layout, Product Definition, Python
(Locations: Beijing, Shanghai, Jinan, Taipei)
Responsible for identifying and understanding customer needs and opportunities, proposing Astera Labs solutions which provide clear value to the customer, and providing hands-on design-in support. You will drive innovation by gathering customer requirements, defining new products, and working with some of the brightest engineers in the industry.
- Experience: BSEE/MSEE; 5+ years, 8+ years for senior/lead positions
- Keywords: FAE, Applications, Schematic, Layout, Product Definition, Python
(Locations: San Francisco Bay Area, Pacific Northwest, Texas)
Responsible for identifying and understanding customer needs and opportunities, proposing Astera Labs solutions which provide clear value to the customer, and providing hands-on design-in support. You will drive innovation by gathering customer requirements, defining new products, and working with some of the brightest engineers in the industry.
- Experience: BSEE/MSEE; 5+ years, 8+ years for senior/lead positions
- Keywords: FAE, Applications, Schematic, Layout, Product Definition, Python
(Locations: Beijing, Shanghai, Jinan, Taipei)
Responsible for identifying target customers, size of Astera Labs sales opportunities and outlining steps to effectively engage and develop relationships within key influencers in R&D, Procurement, Executive level GM/CTO. You will work closely with Field Sales Engineers (FAEs) and the sales management team to develop an account strategy to effectively engage with leading cloud service providers, server and networking OEMs to design in Astera Labs’ portfolio of connectivity products.
- Experience: Bachelor’s degree, preferred engineering and MBA; 5+ years, 8+ years for senior/lead positions
- Keywords: Sales, Business Development, Strategy Planning
Responsible for developing and performing post-silicon validation tests using advanced high-speed test equipment and scalable automation platforms. The validation team holds customers’ system requirements in the highest regard and is solely responsible for certifying a product’s conformance to this high bar. Validation is a data-driven and spec-driven function with heavy automation to support this approach.
- Experience: BSEE/MSEE; 5+ years, 8+ years for senior/lead positions
- Keywords: Python, Design-of-Experiments, Validation, BERT, Scope, Python (again)
Responsible for software architecture and development of firmware/system software for network and storage controller management protocols. Extensive knowledge of C, Embedded software, Ethernet networking. Excellent team player with solid communication skills.
- Experience: BSEE/MSEE; 5+ years, 8+ years for senior/lead positions
- Keywords: TCP/IP, RTOS, JTAG, ARM, Python.
Responsible for developing and overseeing SoC test strategy, interacting with manufacturing partners, writing and implementing ATE programs, and owning the product from initial samples all the way through high-volume production ramp.
- Experience: BSEE/MSEE; 5+ years, 8+ years for senior/lead positions
- Keywords: Test, Scan, MEMBIST, ATE, Probe
Responsible for architecture and implementation of low-level software for in-fleet diagnostics, system qualification, and continuous monitoring for server, storage, and networking equipment or subsystems. Demonstrated leadership and communication skills. Working knowledge of BIOS functions as it relates to BMC.
- Experience: BSCS/MSCS; 5+ years developing Python Packages and C Libraries
- Keywords: Python, C, GitHub, BMC
Responsible for overall chip architecture, including IP integration, working with IP vendors for embedded processors, high bandwidth IO and memory interconnect with multiple clock domains. Demonstrated leadership and communication skills.
- Experience: MSEE/PhD; 10+ years developing communication and/or processor SoCs
- Keywords: Accelerators, PCIe, NVMe, Ethernet networking
Responsible for the development of Analog front end, DSP equalization, and Clock-Data-Recovery circuits for 10s of GHz to address high bandwidth IO and memory interconnects in Data Center applications. Excellent team player with solid communication skills with recent experience with advanced Fin-FET technologies.
- Experience: MSEE/PhD; 5+ years, 8+ years for senior/lead positions
- Keywords: PCIe, Ethernet networking, DDR, AFE, CTLE, DFE, VGA, ADC, DAC, CDR, PLL, VCO
Responsible for all implementation phases from netlist to GDSII. Experience with Fin-FET processes required. Hands-on experience with place and route, timing closure, physical verification and tapeout checks is a must. Deep knowledge of industry standard tools. Knowledge of DFT architecture and scan insertion preferred. Must have solid communication skills.
- Experience: MSEE/BSEE; 8+ years
- Keywords: TSMC, Fin-FET, PrimeTime, ICC, TetraMAX, Innovus, Tempus, Modus, etc.