Leo Interop

Ensuring plug-and-play interoperability for the growing CXL® ecosystem

Deploy CXL-attached memory at scale with confidence

Rigorous testing of Leo Memory Controllers with industry-leading hosts, memory, and operating systems
Comprehensive testing including PCIe electrical, memory, CXL® compliance and system level for end-to-end coverage
Extensive testing with COSMOS software suite for Link, Fleet and RAS telemetry and diagnostics

How We Test

Leo Memory Controllers are tested from the physical layer to the system level in real-world use cases to ensure seamless interoperability.

Interop Bulletins

Leo Interop with Intel Xeon 6 Processors

Astera Labs has completed successful interop testing between Leo CXL Smart Memory Controllers and Intel Xeon 6 Processors.

Interop Testing with Leo and DDR5-5600 RDIMMs

Learn about industry-first interoperability testing between Leo and DDR5-5600 RDIMMs from Micron, Samsung, and SK hynix.

Interop Testing with CXL® 1.1 Host CPUs & DDR5 Memory

Learn about interop testing with 64GB DDR5 RDIMMs from Micron, Samsung, and SK Hynix, each of which are tested with CXL® 1.1-capable CPUs from AMD and…

Hardware and Software Coverage

Example Tests

CXL® Compliance Tests

PCIe Electrical Testing
Transaction Layer Testing
Arbitrator and Multiplexer
Power Management Tests
Reset and Initialization Tests

System & Memory Tests

DDR Tests
Stress Tests
Traffic Tests
Security Tests
Reliability, Availability, and Serviceability

Request interop report

PCIe® Retimers vs. Redrivers: Ensuring Signal Integrity for AI Infrastructure

PCIe® technology serves as the backbone of data center communication in AI infrastructure. The latest PCIe standards deliver unprecedented data transfer rates—32 GT/s with PCIe 5.0 and 64 GT/s with PCIe 6.0. However, as speeds increase, so do the challenges in maintaining clean, reliable signals over longer distances or complex paths. Higher data rates make signals more susceptible to…

Extending Our Connectivity Leadership: Industry’s First End-to-End PCIe® over Optics Demo

The Generative AI revolution is reshaping all industries and redefining what’s possible in every aspect of our lives. Behind the scenes, the rapid pace of innovation is creating significant challenges for data center infrastructure, including:Exploding demand for AI processing resources that must be interconnected across the data center due to the need for Large Language Models to…

The Long and Short of AI: Building Scalable Data Centers in the PCIe® 6.x Era

By Abhishek Wadhwa, Senior Field Applications Engineer The rise of artificial intelligence (AI) and Generative AI are transforming how we interact with technology. From healthcare to business efficiency and groundbreaking research, AI and Generative AI are making waves. These AI marvels rely on vast amounts of hardware and infrastructure to function. As such, data centers are undergoing…

Astera Labs Opens New R&D Hub in Bengaluru to Drive AI and Cloud Innovation

Dr. Shivananda Koteshwar to lead the company’s India operations and spearhead development of innovative connectivity solutions for AI and cloud infrastructureSANTA CLARA, CA, U.S. – September 11, 2024 – Astera Labs, Inc. (Nasdaq: ALAB), a global leader in semiconductor-based connectivity solutions for AI and cloud infrastructure, today announced the official opening of its…

Astera Labs to Participate in the Deutsche Bank 2024 Technology Conference

SANTA CLARA, Calif.–Aug. 21, 2024— Astera Labs (Nasdaq: ALAB), a global leader in semiconductor-based connectivity solutions for AI and cloud infrastructure, today announced that it will participate in the Deutsche Bank 2024 Technology Conference on Aug. 29, 2024. Astera Labs’ presentation is scheduled for 12:30 pm PT. A webcast of the session will be made available on Astera Labs’…

Astera Labs’ AI Inferencing Demo with Leo CXL® Smart Memory Controllers Wins FMS Best of Show Award

Joint demo delivered 40% faster time-to-insights and 40% lower CPU utilizationAstera Labs, alongside its ecosystem partners, Supermicro and MemVerge, has won the Future of Memory and Storage (FMS) 2024 Most Innovative Technology Award. At FMS 2024, we jointly demonstrated how AI inferencing can gain significant benefits using CXL®-attached memory.Astera Labs is a second time winner,…

Astera Labs Announces Financial Results for the Second Quarter of Fiscal Year 2024

Record quarterly revenue of $76.9 million, up 18% QoQ and up 619% YoYMultiple secular trends, design wins across diverse AI platform architectures, and increasing average dollar content position the Company to outpace industry growthSANTA CLARA, CA, U.S. – August 6, 2024 – Astera Labs, Inc. (Nasdaq: ALAB), a global leader in semiconductor-based connectivity solutions for cloud…

Leo Interop with Intel Xeon 6 Processors

Astera Labs has completed successful interop testing between Leo CXL Smart Memory Controllers and Intel Xeon 6 Processors to deliver CXL 2.0 capabilities. The testing also validated 96GB and 128GB DDR5-4800/5600 memory modules from all major memory vendors.

PCIe® 6.x Technology Demo with Aries 6

See a live demo of PCIe® 6.x technology with Aries 6 – the third generation of our Aries PCIe/CXL® Smart DSP Retimer family.

AI Inferencing Demo with CXL®-Attached Memory: FMS 2024

This award-winning demo between Astera Labs, Supermicro, and MemVerge shows how AI inferencing can gain significant benefits using CXL® attached memory.