Leo CXL Smart Memory Controller – the industry’s first CXL memory expansion, pooling and sharing solution – has undergone rigorous interoperability testing with a broad range of hosts, memory, and operating systems. Check out our latest Interop Lab Bulletin to learn more.
Now you can deploy CXL with confidence. At Astera Labs, we understand that meeting compliance standards and supporting plug-and-play interoperability are critical for our customers. That’s why we have partnered with industry leaders to implement end-to-end CXL tests and tools to minimize interoperation risk, reduce system development costs, and accelerate time-to-market.
Interop Bulletins
Interop Bulletin 2: Interop Testing with Leo Memory Connectivity Platform and DDR5-5600 RDIMMs
In our Interop Bulletin, we demonstrated interoperability between our Leo CXL Memory Connectivity Platform and DDR5-5600 RDIMMs from Micron, Samsung, and SK hynix.
Interop Testing with CXL 1.1 Host CPU’s and Popular DDR5 Memory Module
After establishing the foundation of our rigorous testing, we worked with our customers to determine the most popular memory configurations for their systems and applications, to which we’ve included in our initial interop reports. We include 64GB DDR5-4800 RDIMMs from Micron, Samsung, and SK Hynix, each of which are tested with CXL 1.1-capable CPUs from AMD and Intel.
Design with Confidence
The Cloud-Scale Interop Lab testing process establishes robust interoperability between Leo CXL Smart Memory Controllers and industry-leading CPUs and memory, allowing you to reduce risk in designing CXL-based architectures, decrease your development time and effort, and deploy CXL-attached memory with confidence.
Hardware and Software Coverage
Example Tests
CLX Compliance Tests
- PCIe Electrical Testing
- Transaction Layer Testing
- Arbitrator and Multiplexer
- Power Management Tests
- Reset and Initialization Tests
System & Memory Tests
- DDR Tests
- Stress Tests
- Traffic Tests
- Security Tests
- Reliability, Availability and Serviceability