In this PCI-SIG® hosted technical webinar, Astera Labs’ engineers explore the changes between PCIe 4.0 and PCIe 5.0 specifications, including signal integrity and system design challenges, where the right balance must be found between PCB materials, connector types and the use of signal conditioning devices for practical compute topologies. Through an objective analysis, the goal is to provide the audience with a methodology to optimize signal and link integrity performance, present best practices for system board design to support PCIe 5.0 technology applications, and test for system level interoperation.
The upgrade from PCIe 4.0 to PCIe 5.0 doubles the bandwidth from 16GT/s to 32GT/s but also suffers greater attenuation per unit distance, despite the PCIe 5.0 specification increasing the total insertion loss budget to 36dB. After deducting the loss budget for CPU package, AIC, and CEM connector, merely 16dB system board budget remains. Within the remaining budget, engineers need to consider safety margin for board loss variations due to temperature and humidity.
Astera Labs explains the signal integrity challenges of PCIe 5.0 and the corresponding OCP system design challenges, where the right balance must be found between PCB materials, connector types, and the use of signal conditioning devices for practical compute topologies: CPU-to-AIC with one/two connectors, JBOG accelerator module baseboard, etc.
Flywheels of Innovation – Astera Labs, AWS, Intel and Six Nines Revolutionizing Semiconductor Development in the Cloud
One of our core values is to innovate exponentially, rather than incrementally, in everything we do. Our innovative 100% cloud-based design approach with partners AWS, Intel and Six Nines is yet another example of how Astera Labs delivers high quality results to our customers on time, meeting spec and within budget. Learn more about our journey in this video produced by AWS and Intel.
Astera Labs Partners with Intel Capital to Accelerate Deployment of Connectivity Solutions for Computation-Intensive Workloads
Jitendra Mohan, Chief Executive Officer of Astera Labs, discusses our collaboration with Intel Capital and continued mission to solve connectivity bottlenecks throughout the data center. Solutions such as our Aries Smart Retimer for PCIe 4.0 and 5.0 are key for our customers to easily design systems that overcome complex performance challenges of intelligent systems.
The design solution space for high-speed serial links is becoming increasingly complex with increasing data rates, diverse channel topologies, and tuning parameters for active components. PCI Express® 5.0, at 32 GT/s, is a particularly relevant example of an application whose design solution space can be a daunting problem to tackle, given the performance-cost requirements of its end equipment. This paper is intended to help system designers navigate these design challenges by providing a how-to guide for defining, executing, and analyzing system-level simulations, including PCIe 5.0 Root Complex (RC), Retimer, and End Point (EP).
Astera Labs Chief Business Officer, Sanjay Gajendra, and Head of Engineering Operations, Nate Unger, introduce the Aries Smart Retimer portfolio for PCIe® 4.0 and 5.0 applications.
Aries PCIe Smart Retimer — a low-power, low-space, and low-latency solution, supports a wide topology of applications, along with bifurcation capabilities. Advanced features, such as built-in diagnostics and fleet management capability, enable easy system bring-up and large cloud deployment.
The Aries Smart Retimer portfolio doubles the reach and achieves plug-and-play interoperability with CPUs and endpoints while meeting PCI-SIG® compliance.
Jitendra Mohan, Chief Executive Officer of Astera Labs, and Sanjay Gajendra, Chief Business Officer of Astera Labs, introduce Astera Labs’ goal of removing bottlenecks in data-centric systems.
Heterogeneous computing and workload-optimized platforms are redefining the connectivity backbone in the next generation of servers. This new backbone requires faster and lower-latency interconnects. The company’s product portfolio includes system-aware semiconductor-integrated circuits, boards, and services to enable robust PCIe® connectivity. Partnering with leading processor vendors, cloud service providers, seasoned investors and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in compute-intensive workloads.
In this demonstration, Head of Systems and Applications Casey Morrison, showcases Astera Labs’ PCIe® Smart Retimer in a Gen 4.0 SSD application.
The proliferation of heterogeneous computing and distributed workloads requires more SSDs running at a faster speed, causing signal integrity challenges. The Aries Smart Retimer can be used to improve the performance of SSD, ensuring SSDs are operating at the maximum PCIe Gen 4.0 speed.
In this video, Casey Morrison gives a quick tutorial on PCIe® Retimers – What do they do? When to use them? What key features to look for? PCI-SIG compliance requirements, etc.
Signal-integrity challenges will be significant in PCIe Gen 4.0 and Gen 5.0 due to increased data rates. A PCIe Retimer is a cost-optimized option to provide more margins and enable a robust link. Compliance tests meeting electrical and protocol specifications, latency, small total footprint, power consumption, bifurcation capacity, in-band and side-band diagnostics are key features system designers should look for in Retimers.