Deliver high-performance, robust PCIe® link connectivity with optimized thermal efficiency in Universal Baseboard (UBB) designs
UBB Specification Background: As AI models grow in complexity, the demand for larger scale AI systems with distributed processing across multiple GPUs intensifies. To meet this challenge, the Open Compute Project (OCP) community introduced a modular UBB to enable flexible and scalable GPU system configurations while addressing the need for efficient heat dissipation.
Challenges
- Higher PCIe data rates across dense AI server designs make it increasingly difficult to maintain signal integrity over complex board layouts and multiple high-speed connector paths
- As connectivity scales between GPUs, CPUs, switches, and other endpoints, system architects must balance channel performance with power, thermal, latency, and cost constraints
- AI infrastructure teams need flexible connectivity options that align the level of signal conditioning to each deployment while simplifying design decisions and accelerating time-to-market
Solution: Aries PCIe Smart Signal Conditioners
Aries PCIe Smart Retimer
- Purpose-built for demanding AI server channels, delivering robust signal integrity and link stability over long distances for dense GPU baseboards with multiple high-speed connectors
- Low latency with a compact footprint for optimized performance, power consumption, and thermal efficiency
- Real-time lane, link, and device health monitoring and management features with Astera Labs’ COSMOS suite that provides comprehensive diagnostics and telemetry
Aries PCIe Smart Redriver
- Designed for AI platforms that need dependable signal conditioning across complex, connector-rich server and accelerator designs
- Delivers power-efficient approach to improving channel performance while optimizing system cost, footprint, and thermal design
- Adds built-in signal visibility, adaptive equalization, and diagnostics through Astera Labs’ COSMOS software suite to simplify bring-up and improve ongoing link observability
- Extends the Astera Labs connectivity portfolio with pin-compatible design flexibility, helping customers move between levels of signal conditioning without a board redesign
Both solutions benefit from rigorous interoperability testing in our Cloud-Scale Interop Lab with leading GPU, CPU, PCIe switch, network, and storage endpoints to minimize interoperation and accelerate time-to-market.
