PCI-SIG

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PCI Express® 5.0 Architecture Channel Insertion Loss Budget

The upgrade from PCIe® 4.0 to PCIe 5.0 doubles the bandwidth from 16GT/s to 32GT/s but also suffers greater attenuation per unit distance, despite the PCIe 5.0 specification increasing the total insertion loss budget to 36dB. After deducting the loss budget for CPU package, AIC, and CEM connector, merely 16dB system board budget remains. Within the remaining budget, engineers need to consider safety margin for board loss variations due to temperature and humidity.

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PCIe Retimers to the Rescue Webinar: PCI Express® Specifications Reach Their Full Potential

In this PCI-SIG® hosted webinar, Kurt Lender of Intel and Casey Morrison of Astera Labs offer solutions to address signal-integrity and channel insertion loss challenges to ensure the full potential of the increased bandwidth offered by PCIe® Gen 4.0 and 5.0 are achieved.

As PCIe specifications continue to double the transfer rates of previous generations, the technology can address various needs for demanding applications, while signal-integrity and channel insertion loss challenges arise as well. Retimers are mixed-signal analog/digital devices that are protocol-aware and able to fully recover data, extract the embedded clock and retransmit a fresh copy of the data using a clean clock. These devices are fully defined in the PCI Express base specification, including compliance testing, and are used to combat issues that PCI Express faces.