PCI Express® (PCIe®) technology is the most important high-speed serial bus in servers. Due to its high bandwidth and low latency characteristics, PCI Express architecture is widely used in various server interconnect scenarios. At the same time, with the rapid development of heterogeneous computing, the data throughput requirements in the server system are becoming higher and higher. Two years after the release of the PCIe 4.0 specification, the PCIe 5.0 specification was officially released in May 2019. PCIe 5.0 technology still uses the same 128b / 130b coding scheme, and the symbol rate increased from 16 GT/s to 32 GT/s. In keeping with tradition, the PCIe 5.0 specification is backwards compatible with lower-speed PCIe generations.
In this video, Casey Morrison gives a quick tutorial on PCIe® Retimers – What do they do? When to use them? What key features to look for? PCI-SIG compliance requirements, etc.
Signal-integrity challenges will be significant in PCIe Gen 4.0 and Gen 5.0 due to increased data rates. A PCIe Retimer is a cost-optimized option to provide more margins and enable a robust link. Compliance tests meeting electrical and protocol specifications, latency, small total footprint, power consumption, bifurcation capacity, in-band and side-band diagnostics are key features system designers should look for in Retimers.
In this PCI-SIG® hosted webinar, Kurt Lender of Intel and Casey Morrison of Astera Labs offer solutions to address signal-integrity and channel insertion loss challenges to ensure the full potential of the increased bandwidth offered by PCIe® Gen 4.0 and 5.0 are achieved.
As PCIe specifications continue to double the transfer rates of previous generations, the technology can address various needs for demanding applications, while signal-integrity and channel insertion loss challenges arise as well. Retimers are mixed-signal analog/digital devices that are protocol-aware and able to fully recover data, extract the embedded clock and retransmit a fresh copy of the data using a clean clock. These devices are fully defined in the PCI Express base specification, including compliance testing, and are used to combat issues that PCI Express faces.