Smart Retimers

Videos

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Introducing Aries 6 Smart DSP Retimers: First Look Demo

Get your first look at a live demonstration of how the third generation Aries Smart DSP Retimers can extend robust, low-power PCIe 6.x/CXL 3.x reach in complex AI topologies.

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Unlock Peak Performance for Storage Applications with Aries PCIe/CXL Smart DSP Retimers

At Flash Memory Summit 2023, we demonstrated how to unlock peak performance in a storage application with our Aries PCIe/CXL Smart Retimers and the storage-optimized X13 BigTwin server from Supermicro.

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Astera Labs at TSMC China Technology Symposium – June 2023 (Chinese)

Astera Labs’ Head of Sales and Operations for Asia, Campbell Kan, shares details on our partnership with TSMC. We recently had the opportunity to demonstrate our Aries Smart Retimers and Leo Memory Connectivity Platform – solutions optimized to enable compute-intensive generative AI – at TSMC’s China Technology Symposium.

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Extend reach with Aries Smart Retimers

Learn how our Aries Smart Retimers extend reach and overcome signal integrity for complex topologies with advanced diagnostics features for PCIe 4.0/ 5.0 and CXL.

Articles & Insights

Cloud Infrastructure Fleet Management Made Easy With COSMOS

Large server deployments for Artificial Intelligence (AI) and general-purpose computing in hyperscale data centers provide enormous benefits in terms of raw compute power, efficiency, and cost amortization. The on-demand nature and low up-front cost of cloud computing is attractive to an increasing number of enterprises. However, managing such a large fleet of systems presents complex… Read More »

Astera Labs’ Flexible CXL Product Suite Enables Low-Latency Memory Expansion

Artificial intelligence (AI) is the single most transformative technology impacting everyday lives. Data-intensive AI applications as well as in-memory databases, high performance computing (HPC) and high-performance file systems are driving the need for faster interconnects between CPUs, GPUs, TPUs, DPUs, SmartNICs and FPGAs. Low latency is also critical, especially for memory interconnects. Compute Express Link™… Read More »

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Breaking Through the Memory Wall

The term “memory wall” was first coined in 1994 to define what was becoming an obvious problem at the time: processor performance was outpacing memory interconnect bandwidth. In other words, memory access was limiting compute performance. Almost 30 years later this statement still holds true, especially in memory-intensive applications such as artificial intelligence (AI) where… Read More »

Astera Labs Delivers Industry-First CXL Interop with DDR5-5600 Memory Modules

Earlier this year, we announced the launch of our Cloud-Scale Interop Lab for CXL to provide robust interoperability testing between our Leo Memory Connectivity Platform and a growing ecosystem of CXL supported CPUs, memory modules and operating systems. By providing this critical testing, we enable customers to deploy CXL-attached memory with confidence by minimizing interoperational… Read More »