“We are in a tremendous growth phase in every aspect of our business and the new Astera Labs Vancouver location will be instrumental in driving our continued expansion as a company and as the industry leader in advanced data and memory connectivity,” said Sanjay Gajendra, chief business officer, Astera Labs. “We thank Mayor Mike Hurley and the City of Burnaby for its extraordinary support in getting this new office off the ground, which will accelerate our vision to enable the true potential of AI and Machine Learning in the cloud with our purpose-built intelligent connectivity solutions.”

Astera Labs welcomes the Mayor of Burnaby and the Burnaby Board of Trade President and CEO to celebrate the grand opening of its new state-of-the-art design center and lab in the Greater Vancouver Area.

“Our Leo Memory Connectivity Platform for CXL 1.1 and 2.0 is purpose-built to overcome processor memory bandwidth bottlenecks and capacity limitations in accelerated and intelligent infrastructure,” said Jitendra Mohan, CEO, Astera Labs. “Successful delivery of Leo Smart Memory Controllers, Leo-based hardware board solutions and comprehensive software tools to our partners and customers represents a significant industry-first milestone by paving the way for a seamless, at-scale deployment of memory pooling and expansion in the Cloud.”

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“The new CXL 3.0 Specification doubles bandwidth, enhances fabric management, and expands the scale of heterogenous compute, resulting in significant optimizations for AI and Machine Learning. Astera Labs is proud to collaborate with the CXL Consortium in the development of the new specification and we look forward to leveraging CXL 3.0 to expand our portfolio of purpose-built connectivity solutions.”

Jitendra Mohan, CEO, Astera Labs

“We’re thrilled to officially open our new R&D Design Center in the Toronto Area and expand Astera Labs’ engineering workforce to support our rapid transition from a successful start-up to a mature global company,” said Sanjay Gajendra, chief business officer, Astera Labs. “We thank Markham Mayor Frank Scarpitti for participating in our ribbon cutting ceremony to mark this momentous occasion and look forward to harnessing the region’s rich engineering talent that will shape the future of intelligent connectivity solutions.”

“The City welcomes Astera Labs’ first Research and Development Centre outside of the US’ Silicon Valley to Markham’s innovation corridor — Canada’s second largest tech cluster,” said Frank Scarpitti, Mayor of Markham. “Astera Labs’ investment in technology and product development in the semiconductor vertical is vital to our local economy as it draws on the City’s diverse and dense talent base. We look forward to Astera Labs’ many successes.”

“This is an exciting moment of growth for Astera Labs, and we are thrilled to welcome Sanjay, Richard, and Philip as we continue to mature as a company,” said Sanjay Gajendra, chief business officer for Astera Labs. “With decades of shared experience between these proven industry veterans, I’m confident that they will make an immediate impact throughout the company, support wide-spread expansion of existing product families, and guide development of new purpose-built connectivity solutions in strategic markets.”

“The new UCIe specification enables innovative chiplet solutions to optimize power, performance, cost, and time to market of large SoCs for data centers as well as enhanced resource sharing and pooling across servers,” said Jitendra Mohan, CEO, Astera Labs. “We are excited to support this new industry effort with our proven expertise in intelligent CXL and PCIe interconnects and look forward to expanding our purpose-built connectivity solutions portfolio to include products based on the UCIe standard.”

“PCIe 5.0 and CXL technologies are key building blocks to address the high-speed connectivity requirements of next-generation servers running intelligent workloads in the cloud,” said Jitendra Mohan, CEO, Astera Labs. “Production release and successful cross-vendor interoperability testing of our Aries Smart Retimers will support a smooth transition to higher-bandwidth interconnects with purpose-built fleet management features.”

“I am excited to have Aleksandr expand his role within Astera Labs to lead our hardware engineering team as we expand our focus on providing system and board level connectivity solutions for data-centric applications,” said Jitendra Mohan, chief executive officer for Astera Labs. “Casey’s elevation to the role of chief product officer and Aleksandr’s appointment as vice president of hardware engineering will strengthen the company’s ability to define, drive and deliver compelling solutions for distributing data in intelligent systems.”

“Our new Taurus Smart Cable Module solution tackles hyperscalers’ emerging 50G and 100G/Lane Ethernet design challenges, which impact reach, signal integrity, physical constraints, power budgets and bandwidth utilization,” said Sanjay Gajendra, CBO, Astera Labs. “The Taurus modular approach reduces barriers of adoption in the industry by enabling established cable OEMs to rapidly develop multiple Ethernet solutions for various speed generations, while also allowing cloud service providers to maintain a flexible supply chain of interconnects.”