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Press Releases  |  In the News  |  Industry News

Astera Labs Press Releases

AriesMassProduction

Astera Labs Announces Broad Availability of Aries Smart Retimers for PCIe® 4.0 and 5.0 Interconnects; Launches Cloud-Scale Interop Lab

Aug 12, 2020

“Production release of PT4161L x16 PCIe 4.0 Smart Retimers and active sampling of pin-compatible PT5161L x16 PCIe 5.0 Smart Retimers is a critical milestone for the industry, clearing the way for wide deployment of PCIe solutions,” said Jitendra Mohan, CEO, Astera Labs. “Alongside our products, we are unveiling our Cloud-Scale Interop Lab service which provides the necessary testing infrastructure to our customers to ensure seamless interoperation and robust designs of their PCIe 4.0 and PCIe 5.0 systems.”

Capture

Astera Labs Poised for Rapid Growth with Series B Funding and Manufacturing Partnerships in Place

April 22, 2020

“We are very proud of the significant industry traction for our Aries Smart Retimer Portfolio which has been extensively tested with all major CPU, GPU and PCIe 4.0 endpoints,” said Jitendra Mohan, CEO, Astera Labs. “We look forward to accelerating this momentum by partnering with such a distinguished group of technology and manufacturing heavyweights to develop purpose-built connectivity solutions for data-centric systems.“

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astera-lab

Astera Labs Accelerates PCI Express 5.0 System Deployment in Collaboration with Intel and Synopsys

October 23, 2019

"Astera Labs' Aries Smart Retimer is the industry's first 32GT/s retimer SoC designed to the PCIe 5.0 specification. It doubles the signal reach and achieves plug-and-play interoperation without compromising interconnect topologies even at 32 GT/s speeds."

astera-lab

Astera Labs Introduces World’s First Smart Retimer Portfolio for PCI Express 4.0 and 5.0 Solutions

October 22, 2019

"Rather than taking an incremental approach to adding bandwidth capabilities, we took a ground-up approach to optimize our Retimers for workload-optimized platforms that demand low latency and cloud-scale management capabilities. Built in the cloud, for the cloud, with our Aries portfolio we are pioneering PCIe Smart Retimer solutions for the industry."

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Verification-IP

Astera Labs Verifies Its System-Aware PCI Express 5.0 Smart Retimer Using Avery Design Systems PCIe 5.0 Verification IP

June 18, 2019

"Astera Labs successfully utilized Avery's Peripheral Component Interconnect PCI Express® (PCIe®) 5.0 Verification IP and services to verify its breakthrough system-aware PCIe 5.0 Smart Retimer."

reach-server

Breakthrough Technology from Astera Labs Doubles PCI Express Signal Reach in Servers

May 29, 2019

"Heterogeneous computing and workload-optimized platforms are redefining the connectivity backbone in the next generation of servers. Specialized semiconductors will help enable this high-speed connectivity backbone and accelerate technology adoption."

Press Releases  |  In the News  |  Industry News

Astera Labs in the News

CRN

The 10 Hottest Semiconductor Startups of 2020

Nov 23, 2020

CRN names Astera Labs as one of the hottest semiconductor startups of 2020. With the global semiconductor industry expected to grow sales by 6.2 percent in 2021, Astera Labs’ purpose-built connectivity solutions will be integral for data-centric system designers to overcome performance bottlenecks throughout the data center.

Interested in joining our team of game changing disrupters? Visit the Careers page.

Astera Labs: Purpose Built Connectivity

Astera Labs: Purpose Built Connectivity

August 14, 2020

“We’re building technology to remove connectivity bottlenecks and distribute data in intelligent systems. Processors within a heterogenous compute system can generate and consume lots of data, this requires fast and low-latency interconnects. Our Aries Smart Retimers for PCIe enable 32 gigabit/lane transactions compared to today’s 8 gigabit/lane – this 4x jump in performance is a critical enabler.”

AWS-Intel-Astera-Video

Flywheels of Innovation - Astera Labs, AWS, Intel and Six Nines Revolutionizing Semiconductor Development in the Cloud

May 22, 2020

One of our core values is to innovate exponentially, rather than incrementally, in everything we do. Our innovative 100% cloud-based design approach with partners AWS, Intel and Six Nines is yet another example of how Astera Labs delivers high quality results to our customers on time, meeting spec and within budget. Learn more about our journey in this video produced by AWS and Intel.

IntelCapitalPR

Astera Labs and Intel Capital Partner to Build a Connected Future

May 12, 2020

“Intel Capital identifies and invests in disruptive startups that are working to improve the way we work and live. Intel Capital is excited to work with Astera Labs as we jointly navigate the current world challenges and as we together drive sustainable, long-term growth.”

Watch Jitendra Mohan, Chief Executive Officer of Astera Labs, discusses our collaboration with Intel Capital.

 

CXLpart1

Which Chip Interconnect Protocol is Better?

May 11, 2020

Pulling from deep experience in the connectivity industry, Astera Labs CEO Jitendra Mohan sits down with Semiconductor Engineering to share his perspective on the differences between the Compute Express Link (CXL) and Cache Coherent Interconnect for Accelerators (CCIX) protocols, as well as the need for purpose-built semiconductor chips that offer high-performance, reliability, ease-of-use and intelligent diagnostics.

Part One : Which Chip Interconnect Protocol is Better

Part Two : Choosing between CCIX and CXL

Intel-Capital-Video

Astera Labs Partners with Intel Capital to Accelerate Deployment of Connectivity Solutions for Computation-Intensive Workloads

April 21, 2020

Jitendra Mohan, Chief Executive Officer of Astera Labs, discusses our collaboration with Intel Capital and continued mission to solve connectivity bottlenecks throughout the data center. As Artificial Intelligence and Machine Learning workloads become more mainstream, cloud service providers are deploying heterogeneous compute systems to address these high performance, low-latency demands. Solutions such as our Aries Smart Retimer for PCIe® 4.0 and PCIe 5.0 technology are key for our customers to easily design systems that overcome complex performance challenges.

Revolutionizing-Semiconductor

How Astera Labs is Revolutionizing Semiconductor Product Development—100% in the Cloud

October 21, 2019

“We would never have been able to do the same number of simulations and checks in a traditional environment… In the cloud we could fire 1,000 or 1,500 cores and run verification jobs in parallel with physical design to test the heck out of our chip in a relatively short time. It meant we were able to move very quickly while also ensuring a quality product.”

Retimer-SoC

Synopsys Design and Verification Solutions Enable Astera Labs to Develop Industry's First PCIe 5.0 Retimer SoC

May 30, 2019

"The collaboration represents two game-changing industry milestones: the first large-scale design fully implemented and verified from start to finish on a third-party public cloud, and the industry's first PCIe 5.0 retimer for heterogenous compute and workload-optimized servers."

AI-machine

Connectivity remains central to mainstreaming AI, machine learning workloads

May 23, 2019

"With the benefits of high throughput, low latency, and the ability to carry alternate protocols, PCIe 5.0 is poised to unify server communication and form the connectivity backbone in modular servers for years to come."

explode-in-server

Signal Integrity Challenges Set to Explode in Servers with PCIe 5.0

May 21, 2019

"With the deployment of more servers, each one having more compute density, the challenges associated with moving data between processor, networking and storage nodes cost-effectively are exploding; and signal integrity (SI) will be the primary pain point for these densely-packed systems."

Press Releases  |  In the News  |  Industry News

Industry News & Articles

Techquickie: PCI Express 6.0 is a Big Deal!

[Video] PCIe 6.0 is a Big Deal!

January 11, 2021

“Educational Youtube Channel, Techquickie, covers PCIe 6.0 in detail and discusses some expected design challenges from the future PCIe performance boost.”

Forbes Digital Storage Projections for 2021

Digital Storage Projects for 2021, Part 2

December 29, 2020

“Analyst Tom Coughlin walks through the recent developments and projections for solid state storage and memory, including SSD interconnects, NVMe, NVMe-over-fabric, and CXL.”

Next Platform: Taking the Pulse of the Core HPC Market

Taking the Pulse of the Core HPC Market

December 10, 2020

“Scott Tease, Executive Director of HPC at Lenovo, is interviewed on the status of the High Performance Computing market as well as the outlook of upcoming root complexes and high-speed interconnects such as CXL.”

CXL Consortium Releases Compute Express Link 2.0 Specification

CXL™ Consortium Releases Compute Express Link™ 2.0 Specification

November 10, 2020

“The new 2.0 features, including switching, memory pooling and persistent memory support pave the way for fully disaggregated systems in which pools of accelerators, DRAM and persistent memory storage can be dynamically connected to any one of 16 host servers to meet application demands. These features will enable system designers to invent entirely new types of systems that architects could only dream about just a few years ago.”

ITIGIC: How Do the PCIe Lanes on Your Motherboard Work?

How Do the PCIe Lanes on Your Motherboard Work?

October 23, 2020

“You may be familiar with the purpose of PCIe, but this article explains the physical implementation. From 1 to 16 lanes, PCIe is an instrumental piece of motherboard designs.”

cxl-interconnect-promises-to-move-data-faster-more-efficiently-at-32-gt-s-650x435

New CXL interconnect promises to move data faster, more efficiently at 32 GT/s

August 17, 2020

“CXL builds on PCIe 5.0 infrastructure to reduce complexity and system cost. Host processors and accelerators with CXL support are expected in 2021.”

ED: What's the Difference Going from PCIe 3.0 to 6.0?

Electronic Design: What's the Difference Going from PCIe 3.0 to 6.0?

July 9, 2020

“Each generation of PCIe has a played a prominent role to meet rising performance demands in compute architecture. Look back at the rich history of PCIe technology and what to expect next.”

specification

PCI-SIG® Achieves 32GT/s with New PCI Express® 5.0 Specification

May 29, 2019

"The new specification increases performance in the high-performance markets including artificial intelligence, machine learning, gaming, visual computing, storage and networking."

cxl

CXL Specification 1.0 Released: New Industry High-Speed Interconnect From Intel

March 11, 2019

"[CXL] will use current PCIe 5.0 standards for physical connectivity and electrical standards, providing protocols for I/O and memory with coherency interfaces. The focus of CXL is to help accelerate AI, machine learning, media services, HPC, and cloud applications."

pcie

Getting Ready for 32 GT/s PCIe 5.0 Designs

February 14, 2019

"While the adoption of 32 GT/s PCIe 5.0 technology is on an accelerated pace, SoC designers must understand and handle a few design challenges as they make the shift. 32 GT/s designs have challenging NRZ channels that are extremely lossy and bumpy with many discontinuities, with insertion loss reaching 36 dB and beyond."

primetime

PCIe 5.0 is Ready for Prime Time

January 17, 2019

"PCI-SIG expects [Gen-4 and Gen-5] to co-exist in the market for some time, with PCIe 5.0 used primarily for high-performance devices that crave the ultimate in throughput, like GPUs for AI workloads, and networking applications....less-intense applications, like desktop PCs, are fine with the PCIe 4.0 interface."

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