Aug 12, 2020
“Production release of PT4161L x16 PCIe 4.0 Smart Retimers and active sampling of pin-compatible PT5161L x16 PCIe 5.0 Smart Retimers is a critical milestone for the industry, clearing the way for wide deployment of PCIe solutions,” said Jitendra Mohan, CEO, Astera Labs. “Alongside our products, we are unveiling our Cloud-Scale Interop Lab service which provides the necessary testing infrastructure to our customers to ensure seamless interoperation and robust designs of their PCIe 4.0 and PCIe 5.0 systems.”
May 12, 2020
“Intel Capital identifies and invests in disruptive startups that are working to improve the way we work and live. Intel Capital is excited to work with Astera Labs as we jointly navigate the current world challenges and as we together drive sustainable, long-term growth.”
April 22, 2020
“We are very proud of the significant industry traction for our Aries Smart Retimer Portfolio which has been extensively tested with all major CPU, GPU and PCIe 4.0 endpoints,” said Jitendra Mohan, CEO, Astera Labs. “We look forward to accelerating this momentum by partnering with such a distinguished group of technology and manufacturing heavyweights to develop purpose-built connectivity solutions for data-centric systems.“
October 23, 2019
"Astera Labs' Aries Smart Retimer is the industry's first 32GT/s retimer SoC designed to the PCIe 5.0 specification. It doubles the signal reach and achieves plug-and-play interoperation without compromising interconnect topologies even at 32 GT/s speeds."
October 22, 2019
"Rather than taking an incremental approach to adding bandwidth capabilities, we took a ground-up approach to optimize our Retimers for workload-optimized platforms that demand low latency and cloud-scale management capabilities. Built in the cloud, for the cloud, with our Aries portfolio we are pioneering PCIe Smart Retimer solutions for the industry."
June 18, 2019
"Astera Labs successfully utilized Avery's Peripheral Component Interconnect PCI Express® (PCIe®) 5.0 Verification IP and services to verify its breakthrough system-aware PCIe 5.0 Smart Retimer."
May 30, 2019
"The collaboration represents two game-changing industry milestones: the first large-scale design fully implemented and verified from start to finish on a third-party public cloud, and the industry's first PCIe 5.0 retimer for heterogenous compute and workload-optimized servers."
May 29, 2019
"Heterogeneous computing and workload-optimized platforms are redefining the connectivity backbone in the next generation of servers. Specialized semiconductors will help enable this high-speed connectivity backbone and accelerate technology adoption."
May 22, 2020
One of our core values is to innovate exponentially, rather than incrementally, in everything we do. Our innovative 100% cloud-based design approach with partners AWS, Intel and Six Nines is yet another example of how Astera Labs delivers high quality results to our customers on time, meeting spec and within budget. Learn more about our journey in this video produced by AWS and Intel.
May 11, 2020
Pulling from deep experience in the connectivity industry, Astera Labs CEO Jitendra Mohan sits down with Semiconductor Engineering to share his perspective on the differences between the Compute Express Link (CXL) and Cache Coherent Interconnect for Accelerators (CCIX) protocols, as well as the need for purpose-built semiconductor chips that offer high-performance, reliability, ease-of-use and intelligent diagnostics.
April 21, 2020
Jitendra Mohan, Chief Executive Officer of Astera Labs, discusses our collaboration with Intel Capital and continued mission to solve connectivity bottlenecks throughout the data center. As Artificial Intelligence and Machine Learning workloads become more mainstream, cloud service providers are deploying heterogeneous compute systems to address these high performance, low-latency demands. Solutions such as our Aries Smart Retimer for PCIe® 4.0 and 5.0 technology are key for our customers to easily design systems that overcome complex performance challenges.
October 21, 2019
“We would never have been able to do the same number of simulations and checks in a traditional environment… In the cloud we could fire 1,000 or 1,500 cores and run verification jobs in parallel with physical design to test the heck out of our chip in a relatively short time. It meant we were able to move very quickly while also ensuring a quality product.”
May 29, 2019
"The new specification increases performance in the high-performance markets including artificial intelligence, machine learning, gaming, visual computing, storage and networking."
May 23, 2019
"With the benefits of high throughput, low latency, and the ability to carry alternate protocols, PCIe 5.0 is poised to unify server communication and form the connectivity backbone in modular servers for years to come."
May 21, 2019
"With the deployment of more servers, each one having more compute density, the challenges associated with moving data between processor, networking and storage nodes cost-effectively are exploding; and signal integrity (SI) will be the primary pain point for these densely-packed systems."
March 11, 2019
"[CXL] will use current PCIe 5.0 standards for physical connectivity and electrical standards, providing protocols for I/O and memory with coherency interfaces. The focus of CXL is to help accelerate AI, machine learning, media services, HPC, and cloud applications."
February 14, 2019
"While the adoption of 32 GT/s PCIe 5.0 technology is on an accelerated pace, SoC designers must understand and handle a few design challenges as they make the shift. 32 GT/s designs have challenging NRZ channels that are extremely lossy and bumpy with many discontinuities, with insertion loss reaching 36 dB and beyond."
January 17, 2019
"PCI-SIG expects [Gen-4 and Gen-5] to co-exist in the market for some time, with PCIe 5.0 used primarily for high-performance devices that crave the ultimate in throughput, like GPUs for AI workloads, and networking applications....less-intense applications, like desktop PCs, are fine with the PCIe 4.0 interface."