Astera Labs Launches Cloud-Scale Interop Lab to Enable Seamless Deployment of CXL Solutions at Scale

Astera Labs Appoints Jack Lazar to Board of Directors

Astera Labs Accelerates Company Growth with Series-D Funding and Expanded Board of Directors

Astera Labs Advances CXL Ecosystem with Multiple Partner Demonstrations at #SC22

Astera Labs Advances CXL Technology Ecosystem with 4th Gen AMD EPYC™ Processors

Astera Labs named a Finalist for Most Respected Private Semiconductor Company by Global Semiconductor Alliance

Astera Labs Takes CXL from Promise to Reality with Real Silicon on Customer Platforms at OCP Global Summit 2022

Astera Labs unveils new Vancouver location to further expand its leadership in purpose-built connectivity solutions for AI & ML infrastructure

Astera Labs to host Mayor of Burnaby at grand opening of new Vancouver design center and lab

Astera Labs Enters Pre-Production Phase of Leo Memory Connectivity Platform for CXL-Attached Memory Expansion and Pooling

Astera Labs Welcomes Release of CXL™ 3.0 Specification

Astera Labs Opens New R&D Design Center to Accelerate Product Development by Tapping into Greater Toronto’s Rich Engineering Talent Base

Astera Labs Adds Industry Veterans to Support Rapid Growth and New Product Development

Astera Labs Welcomes Establishment of New UCIe Chiplet Interconnect Standard

Astera Labs Unlocks Next-Gen Cloud Connectivity with Aries PCIe® 5.0 and CXL™ 2.0 Smart Retimers Production Release