Leo Smart Memory Controllers 

Leo X-Series Smart Memory Controllers

Optimize Tokenomics With Fabric-Attached Memory

Leo 2 E-Series and P-Series

Expand, Share, Pool, and Reuse Memory at Scale

Astera Labs Chip and PCB Board – Leo CXL Smart Memory Controller Hardware

Turn Memory Bottlenecks Into Strategic Advantages

  • Improve inference with faster time to first token and more tokens per second
  • Increase memory bandwidth and capacity for agentic AI and volume cloud servers
  • Seamlessly scale memory with diverse accelerator optionality and system topologies
  • Reduce memory costs and alleviate supply constraints with reliable DDR4 reuse
  • Deploy with confidence and optimize operational resilience with COSMOS software

Break Through the Memory Wall

Accelerate AI With CXL®, PCIe®, and Platform-Specific Memory Expansion

time to first token

tokens per second

on memory capacity per Leo device with DDR4 reuse

Leo Smart Memory Controller™ Family

A memory expansion portfolio for any architecture.

Leo X-Series: Fabric-Attached Memory

  • Creates low-latency, high-volume KV cache memory tier closer to the GPU
  • Pairs with industry-leading Scorpio™ 320L PCIe Smart Fabric Switch
  • Supports PCIe-based and other platform-specific GPUs

Leo 2 E-Series: CXL 3.2 Memory Expansion

  • PCIe 6 x16 host connectivity
  • Four DDR4/DDR5 controllers double capacity and bandwidth vs. previous gen
  • Enables redeployment of DDR4 memory in new AI cloud servers

Leo 2 P-Series: CXL 3.2 Memory Pooling and Sharing

  • All the benefits of Leo 2 E-Series plus dual-port PCIe 6 2×8 connectivity
  • Dynamic capacity management for disaggregated memory architectures
  • Unlock stranded memory capacity and improve utilization

Why Use Leo Smart Memory Controllers?

Agentic AI Performance

  • Near-GPU KV Cache

    Create a dedicated tier for offloading long context windows with Leo X-Series.

  • Increased Capacity for Agents

    Expand CPU memory with PCIe 6 x16 host connectivity to handle high-capacity agent context.

  • Accelerator and Architecture Optionality

    Server-level memory expansion and rack-level memory disaggregation for diverse accelerators.

Complete Memory Flexibility

  • Place Memory Where You Need It

    Access memory dynamically through expansion, sharing, and pooling.

  • Platform-Specific Architectures

    Leo X-Series is purpose-built to support accelerators with PCIe or custom interfaces.

  • Multi-Generation DIMM Support

    Deploy reused DDR4 and DDR5 together in new volume server cloud fleets.

Reliable Deployment at Scale

  • Broad Interoperability

    The expanded Leo family is interoperable with major CXL 3 server platforms including AMD, Arm, Intel, and NVIDIA.

  • Fleet-Wide Visibility

    COSMOS provides telemetry and fleet management proven across millions of server deployments.

  • Robust Memory Reuse

    Memory test engines and automated repair engines help identify reliable DIMMs for reuse.

Leo Topologies

Rack-Scale Topologies

Disaggregated Memory Appliance Topologies

AI and General Purpose Server Topologies

Memory Expansion

Integrated KV Cache Server

Memory Sharing and Pooling

Resources

Ordering Information

Product SeriesPart NumberCXLMemoryConfigurationMax speed (MT/s)Form-Factor / Dimensions (mm)
Leo X-Series
PCIe and platform-specific protocols
A1000 PCIe Add-in Card
PCIe and platform-specific protocols
Leo E-SeriesCM61654LE*CXL 3.2 4ch DDR5, 2 DPC / 4ch DDR4, 3 DPC 6400 / 3200 25×49 / 25×49
Leo E-SeriesCM51652LE* CXL 2.0 2ch DDR5, 2 DPC 5600 27×27
Leo P-SeriesCM61654LP* CXL 3.2 4ch DDR5, 2 DPC / 4ch DDR4, 3 DPC 6400 / 3200 25×49 / 25×49
Leo P-SeriesCM51652LP* CXL 2.0 2ch DDR5, 2 DPC 5600 27×27
A2000 CXL Add-in Card A2000* CXL 3.2 8x DDR5 RDIMM slots 6400 PCIe Dual-Width, Air cooled
A2000 CXL Add-in Card A2000* CXL 3.2 12x DDR4 RDIMM slots 3200 PCIe Dual-Width, Air cooled
A1000 CXL Add-in Card A1000* CXL 2.0 4x DDR5 RDIMM slots 5600 PCIe Dual-Width, Air cooled

FAQ

CXL 2.0 is built on the PCIe 5.0 physical layer at 32 GT/s and provides CXL-based memory expansion, with support for memory pooling and sharing in supported system architectures.

CXL 3.0 introduced PCIe 6.0 at 64 GT/s, doubling per-lane speed versus CXL 2.0, plus hardware-coherent memory sharing and multi-level switching. CXL 3.2 builds on those capabilities and primarily adds specification updates focused on device manageability, RAS enhancements, error records, security, and memory management — for example, hot-page monitoring, hardware post-package repair, and enhanced event reporting.

For Astera Labs, the practical difference is that Leo 2 supports both CXL 2.0 and CXL 3.2 operation, enabling backward compatibility while taking advantage of CXL 3.2 bandwidth and capabilities when connected to a CXL 3.x host.

Leo 2 supports PCIe 6.0 x16 or 2×8 connectivity, DDR4 and DDR5 memory, and memory expansion; the P-Series additionally supports memory pooling and sharing.

Agentic applications generate reasoning tokens, call tools and APIs, perform retrieval, and maintain state across multiple turns. That increases KV cache and agent context requirements on GPUs while CPU resources simultaneously handle tokenization, RAG lookups, orchestration, and session state. This puts a strain on memory resources on both the GPU and CPU side.

PCIe mode enables memory access through PCIe memory transactions and can support systems that do not implement the CXL.mem protocol. Leo X-Series Smart Memory Controllers remove the dependency on accelerators having to support CXL.mem protocol and provide fabric-attached memory expansion.

Leo X-Series enables fabric-attached memory for AI inference targeting agentic AI KV cache offload, typically paired with Scorpio Smart Fabric Switches for scale-up connectivity.

Leo 2 E-Series enables CPU-attached memory expansion for in-memory databases, CPU-based agents, and general-purpose servers.

Leo 2 P-Series enables pooled and shared memory for rack-scale capacity utilization across multiple hosts.

Refer to the topologies page for various block diagrams that showcase how Leo integrates into server-level appliances, disaggregated solutions, and scale-up architectures.

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