Smart Retimers

Videos

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Intel Vision 2022

Check out this demo video from Intel Vision featuring our Aries PCIe® Smart Retimers enabling robust PCIe 5.0 connectivity with KIOXIA America, Inc. SSDs and Intel Corporation’s Sapphire Rapids CPU.

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Intel Innovation 2021: Astera Labs, Broadcom, Intel & Samsung PCI Express® 5.0 Demo

Astera Labs joined Broadcom, Intel, and Samsung at Intel Innovation 2021 to demonstrate seamless end-to-end PCI Express® (PCIe®) 5.0 interoperation at 32GT/s.

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Aries CXL™ Smart Retimer Demo: CXL Ecosystem Interop with Intel and Synopsys

Industry’s first demonstration of a fully formed CXL™ link between an Intel root complex, an Aries CXL Smart Retimer and Synopsys end point IP.

Aries Smart Retimers – Enabling PCIe® 5.0 System Level Testing and Low Latency Mode for CXL™
Aries Smart Retimer for PCIe 5.0 and CXL

Learn about Aries Smart Retimers enabling PCIe® 5.0 system level testing on Sapphire Rapids-based platforms using PCIe 4.0 endpoints and sub 10ns latency for CXL™ applications.

Articles & Insights

Cloud Infrastructure Fleet Management Made Easy With COSMOS

Large server deployments for Artificial Intelligence (AI) and general-purpose computing in hyperscale data centers provide enormous benefits in terms of raw compute power, efficiency, and cost amortization. The on-demand nature and low up-front cost of cloud computing is attractive to an increasing number of enterprises. However, managing such a large fleet of systems presents complex… Read More »

Astera Labs’ Flexible CXL Product Suite Enables Low-Latency Memory Expansion

Artificial intelligence (AI) is the single most transformative technology impacting everyday lives. Data-intensive AI applications as well as in-memory databases, high performance computing (HPC) and high-performance file systems are driving the need for faster interconnects between CPUs, GPUs, TPUs, DPUs, SmartNICs and FPGAs. Low latency is also critical, especially for memory interconnects. Compute Express Link™… Read More »

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Breaking Through the Memory Wall

The term “memory wall” was first coined in 1994 to define what was becoming an obvious problem at the time: processor performance was outpacing memory interconnect bandwidth. In other words, memory access was limiting compute performance. Almost 30 years later this statement still holds true, especially in memory-intensive applications such as artificial intelligence (AI) where… Read More »

Astera Labs Delivers Industry-First CXL Interop with DDR5-5600 Memory Modules

Earlier this year, we announced the launch of our Cloud-Scale Interop Lab for CXL to provide robust interoperability testing between our Leo Memory Connectivity Platform and a growing ecosystem of CXL supported CPUs, memory modules and operating systems. By providing this critical testing, we enable customers to deploy CXL-attached memory with confidence by minimizing interoperational… Read More »