The term “memory wall” was first coined in 1994 to define what was becoming an obvious problem at the time: processor performance was outpacing memory interconnect bandwidth. In other words, memory access was limiting compute performance. Almost 30 years later this statement still holds true, especially in memory-intensive applications such as artificial intelligence (AI) where training Large Language Models (LLMs) on big datasets in a reasonable timeframe requires ultra-fast memory bandwidth.
Many attempts have been made to break through the memory wall. These have failed to gain widespread deployment because they lacked one or more key attributes:
Memory Wall Breakthrough
Astera Labs’ Leo Memory Connectivity Platform is the first to break through the memory wall with CXL-attached memory. Its hardware-based heterogeneous interleaving capability enables CPUs to spread memory access across the native CPU memory and the CXL-attached memory, dramatically increasing bandwidth while maintaining low latency. For example, a 5th Gen Intel® Xeon® Scalable processor and two Leo controllers can create a single high-bandwidth node of 12, low-latency DDR5-5600 memory channels.
Astera Labs’ Leo Memory Connectivity Platform:
In benchmarks performed in partnership with industry leaders, Astera Labs’ Leo Memory Connectivity Platform boosts memory capacity and bandwidth up to 50% while lowering latency by up to 25% in memory-intensive applications such as AI, computational fluid dynamics, data warehousing, and EDA.
Astera Labs leads the way in memory connectivity and PCIe/CXL interconnect technology. Discover how Leo CXL Smart Memory Controllers as well as Aries PCIe/CXL Smart Retimers can help you break the memory wall and advance your designs.