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There are generally three ways to approach this:

1. Channel Loss Budget Analysis
2. Simulate channel s-parameter in the Statistical Eye Analysis Simulator (SeaSim) tool to determine if post-equalized eye height (EH) and eye width (EW) meet the minimum eye opening requirements: ≥15 mV EH and ≥0.3 UI EW at Bit Error Ratio (BER) ≤ 10-12.
3. Consider your cost threshold for system upgrades

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A redriver amplifies a signal, whereas a retimer retransmits a fresh copy of the signal.

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For PCIe 5.0, 36 dB pre channel and 36 dB post channel. So ideally, with one retimer, the total loss from Root Complex to End Point is 72 dB. And with two retimers cascaded, the total loss from Root Complex to End Point is 108 dB, leaving 10-20% margin from a system design point of view.

There is no need to fine tune a retimer EQ setting as it participates in Link Equalization with Root Complex and End Points and automatically fine tunes the receiver EQ.

The maximum number to cascade retimers in a link is 2, which is defined in PCIe specification.

Get a Detailed Explanation on the PCI-SIG blog >

Even when equalization is bypassed, a Retimer will still assert the Retimer Present bit (TS2 symbol 5, bit 4) in 2.5 GT/s data rate so that the Root Complex and EP can learn that a Retimer is present in the link.

There are no “special” considerations. During Equalization, the Retimer’s upstream pseudo port (USPP) and the Endpoint will simultaneously train their receivers, with a total time of 24ms to do this. The will also happen with the downstream pseudo port (DSPP) and the root complex. The timeouts are the same regardless of whether a Retimer is present or not.

Not quite, each port of a packet switch has a full PCIe protocol stack:
Physical Layer, Data Link Layer, and Transaction Layer.

A packet switch has at least one root port and at least one non-root port.

A Retimer, by contrast, has an upstream-facing Physical Layer and a downstream-facing Physical Layer but no Data Link or Transaction Layer.

As such, a Retimer’s ports are considered pseudo ports because a Retimer does not have — nor does it need — these higher-logic layers, the latency through a Retimer is much smaller compared to the latency through a packet switch.

The only notable differences are:

• As with all PCIe 5.0 transmitters, the Retimer’s transmitters must support 32 GT/s precoding when requested by the link partner.
• As with all PCIe 5.0 receivers, the Retimer’s receivers must support Lane Margining in both time and voltage.

A Retimer is required to have the same link width on its upstream-facing port and on its downstream-facing port. In other words, the link widths must match. A Retimer must also support down-configured link widths, but the width must always be the same on both ports.

Redrivers are not defined or specified within the PCIe Base Specification, so there are no formal guidelines for using a Redriver versus using a Retimer. This topic is covered in more detail in this article:

PCI Express® Retimers vs. Redrivers: An Eye-Popping Difference.

A Retimer’s transmitters and receivers, on both pseudo ports, must meet the PCIe Base Specifications. This means that a Retimer can support the full channel budget (nominally 36 dB at 16 GHz) on both sides — before and after the Retimer. Calculating the insertion loss (IL) budget should be done separately for each side of the Retimer, and channel compliance should be performed for each side as well, just as you would do for a Retimer-less Root-Complex-to-Endpoint link.

Redrivers and Retimers are active components which impact the data stream: their package imposes signal attenuation, their active circuits apply boost, and (in the case of Retimers) clock and data recovery. As such, there is no way to truly disable these components and still have data pass through. When disabled, no data will pass through a Redriver or Retimer.

1. Determine if a Retimer is needed based on different PCB materials
2. Define a simulation space, and identify worst-case conditions (temperature, humidity, impedance, etc.), minimum set of parameters (e.g., Transmitter Presets)
3. Define the evaluation criteria, such as minimum eye height/width
4. Execute and analyze results

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Bit error rate (BER) is the ultimate gauge of link performance, but an accurate measure of BER is not possible in relatively short, multi-million-bit simulations.

Instead, this analysis suggests the following pass/fail criteria, which consist of two rules:

1. 1. A link must meet the receiver’s eye height (EH) and eye width (EW) requirements
   2. A link must meet criteria 1 for at least half of Tx Preset settings (≥5 out of 10)

• Criteria 1 establishes that the there is a viable set of settings, which results in the desired BER. The specific EH and EW required by the receiver is implementation-dependent.
• Criteria 2 ensures that the link has adequate margin and is not overly sensitive to the Tx Preset setting.

View Signal Integrity Challenges for PCIe 5.0 OCP Topologies Video >

Use IBIS model and time domain simulations.