AsteraLabs-Blue-Grey-Hz
  • Applications
  • Products
    • Product Overview

      Built in the cloud, for the cloud.

      • Hardware Solutions
      • Design Services
      • Buy and Sample
    • Smart Retimers
      • Aries PCIe®/CXL™ Smart Retimers

        Industry-proven Smart Retimers for PCI Express® (PCIe) 4.0, PCIe 5.0, and Compute Express Link™ (CXL) systems

    • Smart Cable Modules
      • Taurus Ethernet Smart Cable Modules™

        Overcome reach, signal integrity, and bandwidth utilization issues for 100G/Lane Ethernet connectivity

    • CXL Memory Platform
      • Leo CXL Memory Connectivity Platform Pre-production

        CXL-attached memory expansion, pooling, and sharing for cloud servers

  • Cloud-Scale Interop Lab
    • Aries PCIe/CXL Smart Retimers

      Learn how Astera Labs enables you to deploy PCIe and CXL systems with confidence.

    • Leo CXL Memory Connectivity Platform

      Learn how Astera Labs enables you to deploy CXL-attached memory with confidence.

  • Technology Insights
    • Articles

      Browse our knowledge base articles for information about our products and technologies.

    • Video Center

      Explore our educational and technical video center to support your design needs.

    • Document Library

      Find app notes, white papers and more in our technical resource library.

    • FAQs

      Find answers to the most frequently asked questions about our products and technologies.

    • Webinars

      Created by engineers for engineers, our webinar series explores the most important topics related to hyperscale datacenters.

  • Careers
  • About
    • About Us
    • Team
    • Support Portal    
    • Quality
    • News & Articles
    • Events
  • Contact

Home » Products » Smart Retimers » Aries PCIe/CXL Smart Retimers

Aries PCIe/CXL Smart Retimers

Home » Products » Smart Retimers » Aries PCIe/CXL Smart Retimers

Aries PCIe®/CXL™ Smart Retimers

Astera Labs delivers industry-proven Smart Retimers that overcome signal integrity issues for PCI Express® (PCIe®) 4.0, PCIe 5.0, and Compute Express Link™ (CXL™) systems.

Aries Smart Retimers are purpose-built 100% in the cloud and for the cloud, offering extensive fleet management capabilities and tested for robust, seamless interoperation in our Cloud-Scale Interop Lab. As the #1 choice for CPU / GPU vendors and cloud operators, Aries is the industry’s most widely-deployed and field-tested PCIe / CXL Retimer portfolio.

  • Purpose-built for high-performance server, storage, cloud, and workload-optimized systems
  • Pin- and register-compatible solutions for PCIe 4.0, PCIe 5.0, and CXL in x16 and x8 lane configurations
  • Flexible link bifurcation supporting 1x16, 2x8, 4x4, 8x2, and other combinations enabling completely independent links
  • Compatible with PCIe 4.0, PCIe 5.0, and CXL specifications as well as the Intel PCIe Standard Retimer Footprint
  • Receiver and Transmitter performance exceeds PCIe Base Specification requirements for robust signal and link integrity
  • Protocol-transparent low-latency modes to achieve maximum possible application performance
  • Supports all PCIe clock topologies: SRIS, SRNS, Common Clock
  • Supports hot-plug, loopback, Receiver Lane Margining, self-test modes, and PRBS test modes
  • Advanced in-band and out-of-band diagnostics for fleet management in large-scale system deployments
  • Full-featured C and Python SDKs for rapid integration of advanced diagnostics features
  • Support for Lane reversal and automatic polarity correction
  • Integrated AC-coupling capacitors reduce solution size and improves signal integrity performance
  • Drop-in upgrade from PCIe 4.0 to PCIe 5.0 and CXL
  • Interop and stress tested with all major CPUs, GPUs, switches, and 30+ Endpoints in our Cloud-Scale Interop Lab.
Download Product Brief
Order Now
More About the Aries Portfolio
    System Block Diagram
    Aries Smart Retimers Typical Application Block Diagram

    Orderable Information

    Aries PCIe Smart Retimers

    Orderable Part NumberDocumentsDescriptionPackageMax PCIe GenPCIe LanesPack QuantityOrderingEco StatusMSL Peak TempProduction Status
    PT5081LRShttps://www.asteralabs.com/wp-content/uploads/2021/03/Astera_Labs_PT5161L_Product_Brief.pdfAstera Labs CXL/PCIe 5.0 x8 Low-Latency Smart Retimer332-pin FC-CSPPCIe 5.0x 8

    180

    Contact Us, https://www.asteralabs.com/product-details/PT5081LRS/https://www.asteralabs.com/wp-content/uploads/2021/01/astera-labs-self-compliance-reach-rohs-halogen.pdfLevel-3-260C-168 HRProduction
    PT5081LRLhttps://www.asteralabs.com/wp-content/uploads/2021/03/Astera_Labs_PT5161L_Product_Brief.pdfAstera Labs CXL/PCIe 5.0 x8 Low-Latency Smart Retimer332-pin FC-CSPPCIe 5.0x 8

    1800

    Contact Us, https://www.asteralabs.com/product-details/PT5081LRL/https://www.asteralabs.com/wp-content/uploads/2021/01/astera-labs-self-compliance-reach-rohs-halogen.pdfLevel-3-260C-168 HRProduction
    PT5081LXShttps://www.asteralabs.com/wp-content/uploads/2021/03/Astera_Labs_PT5161L_Product_Brief.pdfAstera Labs CXL/PCIe 5.0 x8 Low-Latency Smart Retimer332-pin FC-CSPPCIe 5.0 / CXLx 8

    180

    Contact Us, https://www.asteralabs.com/product-details/PT5081LXS/https://www.asteralabs.com/wp-content/uploads/2021/01/astera-labs-self-compliance-reach-rohs-halogen.pdfLevel-3-260C-168 HRProduction
    PT5081LXLhttps://www.asteralabs.com/wp-content/uploads/2021/03/Astera_Labs_PT5161L_Product_Brief.pdfAstera Labs CXL/PCIe 5.0 x8 Low-Latency Smart Retimer332-pin FC-CSPPCIe 5.0 / CXLx 8

    1800

    Contact Us, https://www.asteralabs.com/product-details/PT5081LXL/https://www.asteralabs.com/wp-content/uploads/2021/01/astera-labs-self-compliance-reach-rohs-halogen.pdfLevel-3-260C-168 HRProduction
    PT5161LXLhttps://www.asteralabs.com/wp-content/uploads/2021/03/Astera_Labs_PT5161L_Product_Brief.pdfAstera Labs CXL/PCIe 5.0 x16 Low-Latency Smart Retimer354-pin FC-CSPPCIe 5.0 / CXLx 16

    2400

    Contact Us, https://www.asteralabs.com/product-details/pt5161lxl/https://www.asteralabs.com/wp-content/uploads/2021/01/astera-labs-self-compliance-reach-rohs-halogen.pdfLevel-3-260C-168 HRProduction
    PT5161LXShttps://www.asteralabs.com/wp-content/uploads/2021/03/Astera_Labs_PT5161L_Product_Brief.pdfAstera Labs CXL/PCIe 5.0 x16 Low-Latency Smart Retimer354-pin FC-CSPPCIe 5.0 / CXLx 16

    240

    Contact Us, https://www.asteralabs.com/product-details/pt5161lxs/https://www.asteralabs.com/wp-content/uploads/2021/01/astera-labs-self-compliance-reach-rohs-halogen.pdfLevel-3-260C-168 HRProduction
    PT5161LRLhttps://www.asteralabs.com/wp-content/uploads/2021/03/Astera_Labs_PT5161L_Product_Brief.pdfAstera Labs CXL/PCIe 5.0 x16 Low-Latency Smart Retimer354-pin FC-CSPPCIe 5.0x 16

    2400

    Contact Us, https://www.asteralabs.com/product-details/pt5161lrl/https://www.asteralabs.com/wp-content/uploads/2021/01/astera-labs-self-compliance-reach-rohs-halogen.pdfLevel-3-260C-168 HRProduction
    PT5161LRShttps://www.asteralabs.com/wp-content/uploads/2021/03/Astera_Labs_PT5161L_Product_Brief.pdfAstera Labs CXL/PCIe 5.0 x16 Low-Latency Smart Retimer354-pin FC-CSPPCIe 5.0x 16

    240

    Contact Us, https://www.asteralabs.com/product-details/pt5161lrs/https://www.asteralabs.com/wp-content/uploads/2021/01/astera-labs-self-compliance-reach-rohs-halogen.pdfLevel-3-260C-168 HRProduction
    PT4080LRLhttps://www.asteralabs.com/wp-content/uploads/2021/01/Astera_Labs_PT4080L_Product_Brief.pdfAstera Labs PCIe 4.0 x8 Low-Latency Smart Retimer332-pin FC-CSPPCIe 4.0x 8

    1800

    Contact Us, https://www.asteralabs.com/product-details/pt4080lrl/https://www.asteralabs.com/wp-content/uploads/2021/01/astera-labs-self-compliance-reach-rohs-halogen.pdfLevel-3-260C-168 HRProduction
    PT4080LRShttps://www.asteralabs.com/wp-content/uploads/2021/01/Astera_Labs_PT4080L_Product_Brief.pdfAstera Labs PCIe 4.0 x8 Low-Latency Smart Retimer332-pin FC-CSPPCIe 4.0x 8

    180

    Digi-Key, https://www.digikey.com/en/products/detail/astera-labs-inc/PT4080LRS/13881176?s=N4IgTCBcDaIAoBUAsAGAHCkBdAvkA; Mouser, https://www.mouser.com/ProductDetail/Astera-Labs/PT4080LRS/?qs=%2Fha2pyFadui%252BsY0Drb6169B9G43CO6KNeQYhy4%252B6jzASnE%2FjnFg7Gw%3D%3D; Contact Us, https://www.asteralabs.com/product-details/pt4080lrs/https://www.asteralabs.com/wp-content/uploads/2021/01/astera-labs-self-compliance-reach-rohs-halogen.pdfLevel-3-260C-168 HRProduction
    PT4161LRLhttps://www.asteralabs.com/wp-content/uploads/2020/08/Astera_Labs_PT4161L_Product_Brief.pdfAstera Labs PCIe 4.0 x16 Low-Latency Smart Retimer354-pin FC-CSPPCIe 4.0x 16

    2400

    Contact Us, https://www.asteralabs.com/product-details/pt4161lrl/https://www.asteralabs.com/wp-content/uploads/2021/01/astera-labs-self-compliance-reach-rohs-halogen.pdfLevel-3-260C-168 HRProduction
    PT4161LRShttps://www.asteralabs.com/wp-content/uploads/2020/08/Astera_Labs_PT4161L_Product_Brief.pdfAstera Labs PCIe 4.0 x16 Low-Latency Smart Retimer354-pin FC-CSPPCIe 4.0x 16

    240

    Digi-Key, https://www.digikey.com/en/products/detail/astera-labs-inc/PT4161LRS/13881174?s=N4IgTCBcDaIAoBUAsBGAbCkBdAvkA; Mouser, https://www.mouser.com/ProductDetail/390-PT4161LRS/; Contact Us, https://www.asteralabs.com/product-details/pt4161lrs/https://www.asteralabs.com/wp-content/uploads/2021/01/astera-labs-self-compliance-reach-rohs-halogen.pdfLevel-3-260C-168 HRProduction

    Evaluation Kits

    Evaluation KitImageDocumentsDescriptionMax PCIe GenPCIe LanesPack QuantityOrderingProduction Status
    Eclipse PCIe 4.0 x16 GPU Riser CardEclipse PCIe 4.0 x16 GPU Riser Cardhttps://www.asteralabs.com/wp-content/uploads/2020/11/Astera_Labs_Eclipse_Equinox_Product_Brief.pdfAries PCI Express® 4.0 Smart Retimer Riser CardPCIe 4.0x 16

    1

    Contact Us, https://www.asteralabs.com/products/smart-retimers/pcie-cxl-smart-retimers/order-systems/?system=ECLIPSE-REVAProduction
    Equinox PCIe 5.0 x16 Riser CardEquinox PCIe 5.0 x16 Riser Cardhttps://www.asteralabs.com/wp-content/uploads/2020/11/Astera_Labs_Eclipse_Equinox_Product_Brief.pdfAries PCI Express® 5.0 Smart Retimer Riser CardPCIe 5.0x 16

    1

    Digi-Key, https://www.digikey.com/en/products/detail/astera-labs-inc/EQUINOX-REVA/13982648?s=N4IgTCBcDaIKYEcCuBLAdgewB4gLoF8g; Contact Us, https://www.asteralabs.com/products/smart-retimers/pcie-cxl-smart-retimers/order-systems/?system=EQUINOX-REVAProduction
    COMET-REVACOMET-REVAhttps://www.asteralabs.com/wp-content/uploads/2020/08/Astera_Labs_COMET_Product_Brief.pdfAstera Labs USB-to-I2C Communication Module

    1

    Digi-Key, https://www.digikey.com/en/products/detail/astera-labs-inc/COMET-REVA/13881175?s=N4IgTCBcDaIMYHsC2BTALgAgIYGc0oCcsMAbLAIxxAF0BfIA; Mouser, https://www.mouser.com/ProductDetail/Astera-Labs/COMET-REVA?qs=%2Fha2pyFadujscaAy75Pb6mldQROydX7z1bYmIMd%252Bpx6QoUJRZnAUzA%3D%3D; Contact Us, https://www.asteralabs.com/order-products/?product=COMET-REVAProduction

    You may also order from our distributors >

    Application Notes

    Name Description Type Download
      Fleet Management Made EasyThe Aries Smart Retimer portfolio offers unique features to support multiple PCI Express® and Compute Express Links™ in a system ranging from x16 to x2 width and running at 4.0 (16 GT/s) and 5.0 (32 GT/s) speeds. See how Aries' unique feature set and C-SDK collateral enables a powerful array of Link health monitoring tools for data center server fleet management.White Paper  Request Access
      Aries Compliance TestingThis guide shows how to perform PCIe Transmitter and Receiver compliance tests to ensure your system meets PCI-SIG specifications.Application Note  Request Access
      Aries CScripts TestingThis guide shows how to use the Astera Labs plug-in for CScripts to automate system-level tests of PCIe Links in an Intel-based system. CScripts is a collection of Python scripts which perform tests targeted at exercising different aspects of the PCIe Link Training and Status State Machine (LTSSM).Application Note  Request Access
      Aries IOMTThis guide shows how to use Intel I/O Margin Tool (IOMT) measure I/O performance in an Intel-based server with Aries Smart Retimers’ built-in loopback mode.Application Note  Request Access
      Aries PRBS TestingThis guide shows how to use Aries Smart Retimers’ built-in pseudo-random bit sequence (PRBS) pattern generators and checkers to perform physical-layer stress tests and monitor per-lane margins and bit error rate.Application Note  Request Access
      Aries Pre-RMA ChecklistResolving potential quality issues is a top priority. This step-by-step guide will help to gather critical information in-system prior to initiating an RMA.Application Note  Request Access
      Aries Preset Sweep TestingThis guide shows how to use the Python-SDK to automatically sweep over all Transmitter preset settings to capture the bit error rate (BER), margin information, and other useful performance metrics in a loopback configuration.Application Note  Request Access
      Aries RX Lane MarginingThe PCIe Base Specification has a provision for collecting Receiver margin information from all Receivers in a system during the L0 state of a Link using in-band Control Skip Ordered Sets at 16 GT/s and 32 GT/s. This guide shows how the Aries Smart Retimers supports Lane Margining for both timing and voltage, and an example with the Intel Lane Margining Tool (LMT) is provided.Application Note  Request Access
      Aries Security and RobustnessThis guide covers ways to use the Aries Smart Retimer and the associated C-SDK collateral in a system where security and robustness are critical aspects of maximizing system performance and up-time.Application Note  Request Access
      Aries Self TestThis guide shows how to use the Aries Smart Retimer built-in self-test feature for diagnosing situations where a device is suspected to be damaged or non-functional, possibly due to electrical/thermal over-stress, mechanical damage, etc.Application Note  Request Access

    Why Use Aries Smart Retimers?

    Aries Smart Retimers are robust, easy-to-use, and designed for enterprise fleet management.

    Robustness

    Signal Integrity: Best-in-class SerDes exceeds PCIe specification, supports >32 dB (8 GHz) for both TX and RX, <1 dB (8GHz) package insertion loss, PCIe 5.0 drop-in upgrade


    Thermals: Integrated heat spreader and thermally-optimized materials simplify thermal design


    Interop Testing: Rigorous system testing with 30+ Endpoints and all major Root Complex (Intel, AMD, NVIDIA, etc.)

    Ease-of-Use

    Total Solution Size: Integrated supply decoupling and AC coupling caps reduce solution size >50% and improve signal quality by avoiding vias


    REFCLK: REFCLK repeat feature reduces need for additional CLK buffers


    Flexibility: Firmware upgradable through I2C/EEPROM to add features, expose more diagnostics, adjust protocol for misbehaving Endpoints, and more

    Fleet Management

    Quick Debug: Built-in protocol analyzer with Link state history and timestamps, full non-destructive eye scan for RX Lane margining


    Deep Diagnostics: Firmware-driven link health monitoring to alert BMC of any possible link performance issues


    System Visibility: The Retimers unique position in the middle of the Link means diagnostic tools can help identify system-level issues before they affect customers

    The Difference is Clear

    Aries Smart Retimers are a cost-efficient solution to doubling both bandwidth and reach for complex topologies while maintaining low latency.

    Aries Smart Retimer Benefits
    Aries PCIe 4.0 and PCIe 5.0 Smart Retimer
    Generic PCIe Retimer Issues
    Generic PCIe 4.0 Retimer

    Use Cases

    Server Base Board
    Server Base Board System Block Diagram

    Enabling Low-Cost PCB Material for Next-Gen PCIe® 5.0 Systems​

    NVMe Extender Cards
    NVMe Extender Cards System Block Diagram

    Enabling Multi-Connector and Cabled Topologies

    PCIe® Riser Cards
    Riser Cards 2U / 3U System Block Diagram

    Enabling Multi-Connector, Plug-and-Play Interoperability

    AI Computing
    AI Computing System Block Diagram

    Enabling Complex Topologies for Emerging AI/ML Applications

    Cable Extender Cards
    Cable Extender Cards System Block Diagram

    Enabling Out-of-the-Box PCIe® Expansion​

    Non-Transparent Bridge
    Non-Transparent Bridge

    Enabling Low-Latency CPU-to-CPU Interconnects​

    Videos

    intel-vision-2022-thumbnail
    08 Jun
    Intel Vision 2022

    Check out this demo video from Intel Vision featuring our Aries PCIe® Smart Retimers enabling robust PCIe 5.0 connectivity with KIOXIA America, Inc. SSDs and Intel Corporation’s Sapphire Rapids CPU.

    Deploy Robust PCIe 5.0 Connectivity wit hAries Smart Retimers
    08 Mar
    Deploy Robust PCIe® 5.0 Connectivity with Aries Smart Retimers

    See our Aries Smart Retimers in action via two interoperability demonstrations with key industry partners’ PCIe® 5.0 root complex and endpoints.

    Intel-Innovation-2021
    03 Nov
    Intel Innovation 2021: Astera Labs, Broadcom, Intel & Samsung PCI Express® 5.0 Demo

    Astera Labs joined Broadcom, Intel, and Samsung at Intel Innovation 2021 to demonstrate seamless end-to-end PCI Express® (PCIe®) 5.0 interoperation at 32GT/s.

    • 1
    • 2
    • 3
    • …
    • 5
    • Next »
    Load More loader

    FAQ

    What are the benefits of Aries PCIe Smart Retimers compared to general-purpose retimers?

    Astera Labs Aries PCIe Smart Retimers offer exceptional robustness, ease-of-use and a list of Fleet Management capabilities. Get more details >

    How to determine if a retimer is required?

    There are generally three ways to approach this:

    1. Channel Loss Budget Analysis
    2. Simulate channel s-parameter in the Statistical Eye Analysis Simulator (SeaSim) tool to determine if post-equalized eye height (EH) and eye width (EW) meet the minimum eye opening requirements: ≥15 mV EH and ≥0.3 UI EW at Bit Error Ratio (BER) ≤ 10-12.
    3. Consider your cost threshold for system upgrades

    View Signal Integrity Challenges for PCIe 5.0 OCP Topologies Video >

    What are the differences between Retimers and Redrivers?

    A redriver amplifies a signal, whereas a retimer retransmits a fresh copy of the signal.

    Get a Detailed Comparison >

    How much dB can a Retimer support?

    For PCIe 5.0, 36 dB pre channel and 36 dB post channel. So ideally, with one retimer, the total loss from Root Complex to End Point is 72 dB. And with two retimers cascaded, the total loss from Root Complex to End Point is 108 dB, leaving 10-20% margin from a system design point of view.

    How to fine tune a Retimer EQ setting?

    There is no need to fine tune a retimer EQ setting as it participates in Link Equalization with Root Complex and End Points and automatically fine tunes the receiver EQ.

    What is the maximum number of cascaded Retimers allowed?

    The maximum number to cascade retimers in a link is 2, which is defined in PCIe specification.

    Get a Detailed Explanation on the PCI-SIG blog >

    If equalization can be bypassed in Retimers in PCIe 5.0 architecture, how would an Endpoint (EP) detect if there is a Retimer present?

    Even when equalization is bypassed, a Retimer will still assert the Retimer Present bit (TS2 symbol 5, bit 4) in 2.5 GT/s data rate so that the Root Complex and EP can learn that a Retimer is present in the link.

    Are there special considerations during link training to avoid timeouts when using Retimers?

    There are no “special” considerations. During Equalization, the Retimer’s upstream pseudo port (USPP) and the Endpoint will simultaneously train their receivers, with a total time of 24ms to do this. This will also happen with the downstream pseudo port (DSPP) and the root complex. The timeouts are the same regardless of whether a Retimer is present or not.

    Is a Retimer essentially a two-port PCIe packet switch?

    Not quite, each port of a packet switch has a full PCIe protocol stack:
    Physical Layer, Data Link Layer, and Transaction Layer.

    A packet switch has at least one root port and at least one non-root port.

    A Retimer, by contrast, has an upstream-facing Physical Layer and a downstream-facing Physical Layer but no Data Link or Transaction Layer.

    As such, a Retimer’s ports are considered pseudo ports because a Retimer does not have — nor does it need — these higher-logic layers, the latency through a Retimer is much smaller compared to the latency through a packet switch.

    Is there a difference in Retimer functionality from PCIe 5.0 specification compared to PCIe 4.0 specification?

    The only notable differences are:

    • As with all PCIe 5.0 transmitters, the Retimer’s transmitters must support 32 GT/s precoding when requested by the link partner.
    • As with all PCIe 5.0 receivers, the Retimer’s receivers must support Lane Margining in both time and voltage.
    Other than keeping the same throughput, is a Retimer required to support different link widths for its upstream/downstream ports?

    A Retimer is required to have the same link width on its upstream-facing port and on its downstream-facing port. In other words, the link widths must match. A Retimer must also support down-configured link widths, but the width must always be the same on both ports.

    Why is a Redriver not recommended for the PCIe 5.0 and PCIe 4.0 Specifications?

    Redrivers are not defined or specified within the PCIe Base Specification, so there are no formal guidelines for using a Redriver versus using a Retimer. This topic is covered in more detail in this article:

    PCI Express® Retimers vs. Redrivers: An Eye-Popping Difference.

    Do you suggest putting the Retimer close to the receiver?

    A Retimer’s transmitters and receivers, on both pseudo ports, must meet the PCIe Base Specifications. This means that a Retimer can support the full channel budget (nominally 36 dB at 16 GHz) on both sides — before and after the Retimer. Calculating the insertion loss (IL) budget should be done separately for each side of the Retimer, and channel compliance should be performed for each side as well, just as you would do for a Retimer-less Root-Complex-to-Endpoint link.

    If a Redriver or Retimer is present, is there any way to enable or disable the Redriver or Retimer?

    Redrivers and Retimers are active components which impact the data stream: their package imposes signal attenuation, their active circuits apply boost, and (in the case of Retimers) clock and data recovery. As such, there is no way to truly disable these components and still have data pass through. When disabled, no data will pass through a Redriver or Retimer.

    How to decide between enhanced PCB material or Retimers to solve signal integrity issues?
    1. Determine if a Retimer is needed based on different PCB materials
    2. Define a simulation space, and identify worst-case conditions (temperature, humidity, impedance, etc.), minimum set of parameters (e.g., Transmitter Presets)
    3. Define the evaluation criteria, such as minimum eye height/width
    4. Execute and analyze results

    View Signal Integrity Challenges for PCIe 5.0 OCP Topologies Video >

    How to define evaluation criteria?

    Bit error rate (BER) is the ultimate gauge of link performance, but an accurate measure of BER is not possible in relatively short, multi-million-bit simulations.

    Instead, this analysis suggests the following pass/fail criteria, which consist of two rules:

      1. A link must meet the receiver’s eye height (EH) and eye width (EW) requirements
      2. A link must meet criteria 1 for at least half of Tx Preset settings (≥5 out of 10)
    • Criteria 1 establishes that the there is a viable set of settings, which results in the desired BER. The specific EH and EW required by the receiver is implementation-dependent.
    • Criteria 2 ensures that the link has adequate margin and is not overly sensitive to the Tx Preset setting.

    View Signal Integrity Challenges for PCIe 5.0 OCP Topologies Video >

    How to execute and analyze results?

    Use IBIS model and time domain simulations.

    Have more questions about general topics, such as PCIe 5.0, ordering, quality, etc.? See the full list of FAQs.

    The Evolution of the In-Vehicle Network

    Interconnect technologies will play an important role in the overall connected car story to meet the needs of mass data transfer within the In-Vehicle Network. We have recently seen these types of challenges and a similar evolution in enterprise data centers, where intelligent systems running data-intensive workloads — such as Artificial Intelligence and Machine Learning — have drastically increased the overall design complexity.

    Read More

    PCI Express® 5.0 Architecture Channel Insertion Loss Budget

    The upgrade from PCIe® 4.0 to PCIe 5.0 doubles the bandwidth from 16GT/s to 32GT/s but also suffers greater attenuation per unit distance, despite the PCIe 5.0 specification increasing the total insertion loss budget to 36dB. After deducting the loss budget for CPU package, AIC, and CEM connector, merely 16dB system board budget remains. Within the remaining budget, engineers need to consider safety margin for board loss variations due to temperature and humidity.

    Read More

    Simulating with Retimers for PCIe® 5.0

    The design solution space for high-speed serial links is becoming increasingly complex with increasing data rates, diverse channel topologies, and tuning parameters for active components. PCI Express® (PCIe®) 5.0, at 32 GT/s, is a particularly relevant example of an application whose design solution space can be a daunting problem to tackle, given the performance-cost requirements of its end equipment. This paper is intended to help system designers navigate these design challenges by providing a how-to guide for defining, executing, and analyzing system-level simulations, including PCIe 5.0 Root Complex (RC), Retimer, and End Point (EP).

    Read More

    PCI Express® Retimers vs. Redrivers: An Eye-Popping Difference

    A redriver amplifies a signal, whereas a retimer retransmits a fresh copy of the signal. Retimers provide capabilities such as PCIe® protocol participation, lane-to-lane skew compensation, adaptive EQ, diagnostics features, etc. Therefore, retimers particularly address the need for reach extension in PCIe 4.0 & PCIe 5.0 systems, where increased number of PCIe slots, multiconnectors, and long physical topologies lead to signal integrity (SI) challenges.

    Read More

    The Impact of Bit Errors in PCI Express® Links: The Painful Realities of Low-Probability Events

    PCIe 5.0 ushers in the era of >1Tbps of data bandwidth between two PCIe nodes, and noticeably greater Link Errors and DLLP Retries are likely to occur. By reducing insertion loss (shorter trace, better material, connectors, etc.) or adding retimers to some topologies, system designers can minimize system-level headaches with a target of 1E-17 or lower BER.

    Read More

    Get Interop Testing That's Optimized for Your PCIe and CXL Designs

    Aries Smart Retimers are rigorously tested with all major root complexes and an ever-increasing range of PCIe / CXL endpoints to ensure seamless interoperation and low-risk designs. Each device is put through our exhaustive testing regime that uses the latest systems from Intel and AMD to exercise the PCIe / CXL link to the target endpoint with a battery of tests over thousands of iterations.

    Cloud-Scale Interop Lab

    Hardware Solutions

    Rapidly implement diverse system topologies using our plug-and-play connectivity system boards. Our solutions include:

    • CXL Memory Cards: Increase cloud server performance and reduce total cost of ownership through memory expansion, pooling and sharing.
    • Smart Cable Modules: Active Copper-Based Solution to Address Reach, Signal Integrity and Bandwidth Utilization Issues for 100G/Lane Ethernet Switch-to-Switch and Switch-to-Server Interconnects.
    • Riser Cards: Extend PCIe/CXL technology slots and enable incredibly complex multi-connector topologies.
    • PCIe-Over-Cable Extender Cards: Connect a server head-node to a JBoF or JBoG without sacrificing speed.
    • GPU Booster Cards: Support external graphics (eGPUs) and enhance the gaming experience.

    See our Hardware Solutions >

    Services

    Rapidly design and achieve signal integrity peace of mind and avoid wondering if a PCIe 4.0/5.0, CXL 1.1/2.0 or 100G/Lane Ethernet technology-based design will work. Our team can help develop first-pass design success and accelerate time to market for your systems and boards.

    Contact us for more information about our design and testing services >

    • Aries PCIe/CXL Smart Retimers
    • Taurus Ethernet Smart Cable Modules
    • Leo CXL Memory Connectivity Platform
    • Cloud-Scale Interop Lab
    • Applications
    • Quality
    • Technology Insights
    • Contact Us
    • Careers
    • News & Articles
    • Support Portal    
    Subscribe for Updates
    Please enter your name.
    Please enter a valid email address.
    Subscribe

    Thanks for subscribing! 

    Something went wrong. Please check your entries and try again.

    By submitting this form, you are consenting to receive emails from Astera Labs. You can revoke your consent at any time by using the Unsubscribe link found at the bottom of every email.

    AsteraLabs-WhitewBug-Hz

    Copyright © 2023 Astera Labs, Inc. All rights reserved.

    Site Map I Privacy Policy I Terms of Use | Terms of Sale