Aries PCIe®/CXL™ Smart Retimers
Astera Labs delivers industry-proven Smart Retimers that overcome signal integrity issues for PCI Express® (PCIe®) 4.0, PCIe 5.0, and Compute Express Link™ (CXL™) systems.
Aries Smart Retimers are purpose-built 100% in the cloud and for the cloud, offering extensive fleet management capabilities and tested for robust, seamless interoperation in our Cloud-Scale Interop Lab. As the #1 choice for CPU / GPU vendors and cloud operators, Aries is the industry’s most widely-deployed and field-tested PCIe / CXL Retimer portfolio.
- Purpose-built for high-performance server, storage, cloud, and workload-optimized systems
- Pin- and register-compatible solutions for PCIe 4.0, PCIe 5.0, and CXL in x16 and x8 lane configurations
- Flexible link bifurcation supporting 1x16, 2x8, 4x4, 8x2, and other combinations enabling completely independent links
- Compatible with PCIe 4.0, PCIe 5.0, and CXL specifications as well as the Intel PCIe Standard Retimer Footprint
- Receiver and Transmitter performance exceeds PCIe Base Specification requirements for robust signal and link integrity
- Protocol-transparent low-latency modes to achieve maximum possible application performance
- Supports all PCIe clock topologies: SRIS, SRNS, Common Clock
- Supports hot-plug, loopback, Receiver Lane Margining, self-test modes, and PRBS test modes
- Advanced in-band and out-of-band diagnostics for fleet management in large-scale system deployments
- Full-featured C and Python SDKs for rapid integration of advanced diagnostics features
- Support for Lane reversal and automatic polarity correction
- Integrated AC-coupling capacitors reduce solution size and improves signal integrity performance
- Drop-in upgrade from PCIe 4.0 to PCIe 5.0 and CXL
- Interop and stress tested with all major CPUs, GPUs, switches, and 30+ Endpoints in our Cloud-Scale Interop Lab.
Aries PCIe Smart Retimers
|Orderable Part Number||Documents||Description||Package||Max PCIe Gen||PCIe Lanes||Pack Quantity||Ordering||Eco Status||MSL Peak Temp||Production Status|
|PT5081LRS||https://www.asteralabs.com/wp-content/uploads/2021/03/Astera_Labs_PT5161L_Product_Brief.pdf||Astera Labs CXL/PCIe 5.0 x8 Low-Latency Smart Retimer||332-pin FC-CSP||PCIe 5.0||x 8|
|Contact Us, https://www.asteralabs.com/product-details/PT5081LRS/||https://www.asteralabs.com/wp-content/uploads/2021/01/astera-labs-self-compliance-reach-rohs-halogen.pdf||Level-3-260C-168 HR||Production|
|PT5081LRL||https://www.asteralabs.com/wp-content/uploads/2021/03/Astera_Labs_PT5161L_Product_Brief.pdf||Astera Labs CXL/PCIe 5.0 x8 Low-Latency Smart Retimer||332-pin FC-CSP||PCIe 5.0||x 8|
|Contact Us, https://www.asteralabs.com/product-details/PT5081LRL/||https://www.asteralabs.com/wp-content/uploads/2021/01/astera-labs-self-compliance-reach-rohs-halogen.pdf||Level-3-260C-168 HR||Production|
|PT5081LXS||https://www.asteralabs.com/wp-content/uploads/2021/03/Astera_Labs_PT5161L_Product_Brief.pdf||Astera Labs CXL/PCIe 5.0 x8 Low-Latency Smart Retimer||332-pin FC-CSP||PCIe 5.0 / CXL||x 8|
|Contact Us, https://www.asteralabs.com/product-details/PT5081LXS/||https://www.asteralabs.com/wp-content/uploads/2021/01/astera-labs-self-compliance-reach-rohs-halogen.pdf||Level-3-260C-168 HR||Production|
|PT5081LXL||https://www.asteralabs.com/wp-content/uploads/2021/03/Astera_Labs_PT5161L_Product_Brief.pdf||Astera Labs CXL/PCIe 5.0 x8 Low-Latency Smart Retimer||332-pin FC-CSP||PCIe 5.0 / CXL||x 8|
|Contact Us, https://www.asteralabs.com/product-details/PT5081LXL/||Level-3-260C-168 HR||Production|
|PT5161LXL||https://www.asteralabs.com/wp-content/uploads/2021/03/Astera_Labs_PT5161L_Product_Brief.pdf||Astera Labs CXL/PCIe 5.0 x16 Low-Latency Smart Retimer||354-pin FC-CSP||PCIe 5.0 / CXL||x 16|
|Contact Us, https://www.asteralabs.com/product-details/pt5161lxl/||Level-3-260C-168 HR||Production|
|PT5161LXS||https://www.asteralabs.com/wp-content/uploads/2021/03/Astera_Labs_PT5161L_Product_Brief.pdf||Astera Labs CXL/PCIe 5.0 x16 Low-Latency Smart Retimer||354-pin FC-CSP||PCIe 5.0 / CXL||x 16|
|Contact Us, https://www.asteralabs.com/product-details/pt5161lxs/||Level-3-260C-168 HR||Production|
|PT5161LRL||https://www.asteralabs.com/wp-content/uploads/2021/03/Astera_Labs_PT5161L_Product_Brief.pdf||Astera Labs CXL/PCIe 5.0 x16 Low-Latency Smart Retimer||354-pin FC-CSP||PCIe 5.0||x 16|
|Contact Us, https://www.asteralabs.com/product-details/pt5161lrl/||Level-3-260C-168 HR||Production|
|PT5161LRS||https://www.asteralabs.com/wp-content/uploads/2021/03/Astera_Labs_PT5161L_Product_Brief.pdf||Astera Labs CXL/PCIe 5.0 x16 Low-Latency Smart Retimer||354-pin FC-CSP||PCIe 5.0||x 16|
|Contact Us, https://www.asteralabs.com/product-details/pt5161lrs/||Level-3-260C-168 HR||Production|
|PT4080LRL||https://www.asteralabs.com/wp-content/uploads/2021/01/Astera_Labs_PT4080L_Product_Brief.pdf||Astera Labs PCIe 4.0 x8 Low-Latency Smart Retimer||332-pin FC-CSP||PCIe 4.0||x 8|
|Contact Us, https://www.asteralabs.com/product-details/pt4080lrl/||Level-3-260C-168 HR||Production|
|PT4080LRS||https://www.asteralabs.com/wp-content/uploads/2021/01/Astera_Labs_PT4080L_Product_Brief.pdf||Astera Labs PCIe 4.0 x8 Low-Latency Smart Retimer||332-pin FC-CSP||PCIe 4.0||x 8|
|Digi-Key, https://www.digikey.com/en/products/detail/astera-labs-inc/PT4080LRS/13881176?s=N4IgTCBcDaIAoBUAsAGAHCkBdAvkA; Mouser, https://www.mouser.com/ProductDetail/Astera-Labs/PT4080LRS/?qs=%2Fha2pyFadui%252BsY0Drb6169B9G43CO6KNeQYhy4%252B6jzASnE%2FjnFg7Gw%3D%3D; Contact Us, https://www.asteralabs.com/product-details/pt4080lrs/||Level-3-260C-168 HR||Production|
|PT4161LRL||https://www.asteralabs.com/wp-content/uploads/2020/08/Astera_Labs_PT4161L_Product_Brief.pdf||Astera Labs PCIe 4.0 x16 Low-Latency Smart Retimer||354-pin FC-CSP||PCIe 4.0||x 16|
|Contact Us, https://www.asteralabs.com/product-details/pt4161lrl/||Level-3-260C-168 HR||Production|
|PT4161LRS||https://www.asteralabs.com/wp-content/uploads/2020/08/Astera_Labs_PT4161L_Product_Brief.pdf||Astera Labs PCIe 4.0 x16 Low-Latency Smart Retimer||354-pin FC-CSP||PCIe 4.0||x 16|
|Digi-Key, https://www.digikey.com/en/products/detail/astera-labs-inc/PT4161LRS/13881174?s=N4IgTCBcDaIAoBUAsBGAbCkBdAvkA; Mouser, https://www.mouser.com/ProductDetail/390-PT4161LRS/; Contact Us, https://www.asteralabs.com/product-details/pt4161lrs/||Level-3-260C-168 HR||Production|
|Evaluation Kit||Image||Documents||Description||Max PCIe Gen||PCIe Lanes||Pack Quantity||Ordering||Production Status|
|Eclipse PCIe 4.0 x16 GPU Riser Card||https://www.asteralabs.com/wp-content/uploads/2020/11/Astera_Labs_Eclipse_Equinox_Product_Brief.pdf||Aries PCI Express® 4.0 Smart Retimer Riser Card||PCIe 4.0||x 16|
|Contact Us, https://www.asteralabs.com/products/smart-retimers/pcie-cxl-smart-retimers/order-systems/?system=ECLIPSE-REVA||Production|
|Equinox PCIe 5.0 x16 Riser Card||https://www.asteralabs.com/wp-content/uploads/2020/11/Astera_Labs_Eclipse_Equinox_Product_Brief.pdf||Aries PCI Express® 5.0 Smart Retimer Riser Card||PCIe 5.0||x 16|
|Digi-Key, https://www.digikey.com/en/products/detail/astera-labs-inc/EQUINOX-REVA/13982648?s=N4IgTCBcDaIKYEcCuBLAdgewB4gLoF8g; Contact Us, https://www.asteralabs.com/products/smart-retimers/pcie-cxl-smart-retimers/order-systems/?system=EQUINOX-REVA||Production|
|COMET-REVA||https://www.asteralabs.com/wp-content/uploads/2020/08/Astera_Labs_COMET_Product_Brief.pdf||Astera Labs USB-to-I2C Communication Module|
|Digi-Key, https://www.digikey.com/en/products/detail/astera-labs-inc/COMET-REVA/13881175?s=N4IgTCBcDaIMYHsC2BTALgAgIYGc0oCcsMAbLAIxxAF0BfIA; Mouser, https://www.mouser.com/ProductDetail/Astera-Labs/COMET-REVA?qs=%2Fha2pyFadujscaAy75Pb6mldQROydX7z1bYmIMd%252Bpx6QoUJRZnAUzA%3D%3D; Contact Us, https://www.asteralabs.com/order-products/?product=COMET-REVA||Production|
|Fleet Management Made Easy||The Aries Smart Retimer portfolio offers unique features to support multiple PCI Express® and Compute Express Links™ in a system ranging from x16 to x2 width and running at 4.0 (16 GT/s) and 5.0 (32 GT/s) speeds. See how Aries' unique feature set and C-SDK collateral enables a powerful array of Link health monitoring tools for data center server fleet management.||White Paper||Request Access|
|Aries Compliance Testing||This guide shows how to perform PCIe Transmitter and Receiver compliance tests to ensure your system meets PCI-SIG specifications.||Application Note||Request Access|
|Aries CScripts Testing||This guide shows how to use the Astera Labs plug-in for CScripts to automate system-level tests of PCIe Links in an Intel-based system. CScripts is a collection of Python scripts which perform tests targeted at exercising different aspects of the PCIe Link Training and Status State Machine (LTSSM).||Application Note||Request Access|
|Aries IOMT||This guide shows how to use Intel I/O Margin Tool (IOMT) measure I/O performance in an Intel-based server with Aries Smart Retimers’ built-in loopback mode.||Application Note||Request Access|
|Aries PRBS Testing||This guide shows how to use Aries Smart Retimers’ built-in pseudo-random bit sequence (PRBS) pattern generators and checkers to perform physical-layer stress tests and monitor per-lane margins and bit error rate.||Application Note||Request Access|
|Aries Pre-RMA Checklist||Resolving potential quality issues is a top priority. This step-by-step guide will help to gather critical information in-system prior to initiating an RMA.||Application Note||Request Access|
|Aries Preset Sweep Testing||This guide shows how to use the Python-SDK to automatically sweep over all Transmitter preset settings to capture the bit error rate (BER), margin information, and other useful performance metrics in a loopback configuration.||Application Note||Request Access|
|Aries RX Lane Margining||The PCIe Base Specification has a provision for collecting Receiver margin information from all Receivers in a system during the L0 state of a Link using in-band Control Skip Ordered Sets at 16 GT/s and 32 GT/s. This guide shows how the Aries Smart Retimers supports Lane Margining for both timing and voltage, and an example with the Intel Lane Margining Tool (LMT) is provided.||Application Note||Request Access|
|Aries Security and Robustness||This guide covers ways to use the Aries Smart Retimer and the associated C-SDK collateral in a system where security and robustness are critical aspects of maximizing system performance and up-time.||Application Note||Request Access|
|Aries Self Test||This guide shows how to use the Aries Smart Retimer built-in self-test feature for diagnosing situations where a device is suspected to be damaged or non-functional, possibly due to electrical/thermal over-stress, mechanical damage, etc.||Application Note||Request Access|
Why Use Aries Smart Retimers?
Aries Smart Retimers are robust, easy-to-use, and designed for enterprise fleet management.
Signal Integrity: Best-in-class SerDes exceeds PCIe specification, supports >32 dB (8 GHz) for both TX and RX, <1 dB (8GHz) package insertion loss, PCIe 5.0 drop-in upgrade
Thermals: Integrated heat spreader and thermally-optimized materials simplify thermal design
Interop Testing: Rigorous system testing with 30+ Endpoints and all major Root Complex (Intel, AMD, NVIDIA, etc.)
Total Solution Size: Integrated supply decoupling and AC coupling caps reduce solution size >50% and improve signal quality by avoiding vias
REFCLK: REFCLK repeat feature reduces need for additional CLK buffers
Flexibility: Firmware upgradable through I2C/EEPROM to add features, expose more diagnostics, adjust protocol for misbehaving Endpoints, and more
Quick Debug: Built-in protocol analyzer with Link state history and timestamps, full non-destructive eye scan for RX Lane margining
Deep Diagnostics: Firmware-driven link health monitoring to alert BMC of any possible link performance issues
System Visibility: The Retimers unique position in the middle of the Link means diagnostic tools can help identify system-level issues before they affect customers
The Difference is Clear
Aries Smart Retimers are a cost-efficient solution to doubling both bandwidth and reach for complex topologies while maintaining low latency.
Aries PCIe 4.0 and PCIe 5.0 Smart Retimer
Generic PCIe 4.0 Retimer
Unlock Peak Performance for Storage Applications with Aries PCIe/CXL Smart Retimers
At Flash Memory Summit 2023, we demonstrated how to unlock peak performance in a storage application with our Aries PCIe/CXL Smart Retimers and the storage-optimized X13 BigTwin server from Supermicro.
Astera Labs at TSMC China Technology Symposium – June 2023 (Chinese)
Astera Labs’ Head of Sales and Operations for Asia, Campbell Kan, shares details on our partnership with TSMC. We recently had the opportunity to demonstrate our Aries Smart Retimers and Leo Memory Connectivity Platform – solutions optimized to enable compute-intensive generative AI – at TSMC’s China Technology Symposium.
Astera Labs Aries PCIe Smart Retimers offer exceptional robustness, ease-of-use and a list of Fleet Management capabilities. Get more details >
There are generally three ways to approach this:
- Channel Loss Budget Analysis
- Simulate channel s-parameter in the Statistical Eye Analysis Simulator (SeaSim) tool to determine if post-equalized eye height (EH) and eye width (EW) meet the minimum eye opening requirements: ≥15 mV EH and ≥0.3 UI EW at Bit Error Ratio (BER) ≤ 10-12.
- Consider your cost threshold for system upgrades
A redriver amplifies a signal, whereas a retimer retransmits a fresh copy of the signal.
For PCIe 5.0, 36 dB pre channel and 36 dB post channel. So ideally, with one retimer, the total loss from Root Complex to End Point is 72 dB. And with two retimers cascaded, the total loss from Root Complex to End Point is 108 dB, leaving 10-20% margin from a system design point of view.
There is no need to fine tune a retimer EQ setting as it participates in Link Equalization with Root Complex and End Points and automatically fine tunes the receiver EQ.
The maximum number to cascade retimers in a link is 2, which is defined in PCIe specification.
Even when equalization is bypassed, a Retimer will still assert the Retimer Present bit (TS2 symbol 5, bit 4) in 2.5 GT/s data rate so that the Root Complex and EP can learn that a Retimer is present in the link.
There are no “special” considerations. During Equalization, the Retimer’s upstream pseudo port (USPP) and the Endpoint will simultaneously train their receivers, with a total time of 24ms to do this. This will also happen with the downstream pseudo port (DSPP) and the root complex. The timeouts are the same regardless of whether a Retimer is present or not.
Not quite, each port of a packet switch has a full PCIe protocol stack:
Physical Layer, Data Link Layer, and Transaction Layer.
A packet switch has at least one root port and at least one non-root port.
A Retimer, by contrast, has an upstream-facing Physical Layer and a downstream-facing Physical Layer but no Data Link or Transaction Layer.
As such, a Retimer’s ports are considered pseudo ports because a Retimer does not have — nor does it need — these higher-logic layers, the latency through a Retimer is much smaller compared to the latency through a packet switch.
The only notable differences are:
- As with all PCIe 5.0 transmitters, the Retimer’s transmitters must support 32 GT/s precoding when requested by the link partner.
- As with all PCIe 5.0 receivers, the Retimer’s receivers must support Lane Margining in both time and voltage.
A Retimer is required to have the same link width on its upstream-facing port and on its downstream-facing port. In other words, the link widths must match. A Retimer must also support down-configured link widths, but the width must always be the same on both ports.
Redrivers are not defined or specified within the PCIe Base Specification, so there are no formal guidelines for using a Redriver versus using a Retimer. This topic is covered in more detail in this article:
A Retimer’s transmitters and receivers, on both pseudo ports, must meet the PCIe Base Specifications. This means that a Retimer can support the full channel budget (nominally 36 dB at 16 GHz) on both sides — before and after the Retimer. Calculating the insertion loss (IL) budget should be done separately for each side of the Retimer, and channel compliance should be performed for each side as well, just as you would do for a Retimer-less Root-Complex-to-Endpoint link.
Redrivers and Retimers are active components which impact the data stream: their package imposes signal attenuation, their active circuits apply boost, and (in the case of Retimers) clock and data recovery. As such, there is no way to truly disable these components and still have data pass through. When disabled, no data will pass through a Redriver or Retimer.
- Determine if a Retimer is needed based on different PCB materials
- Define a simulation space, and identify worst-case conditions (temperature, humidity, impedance, etc.), minimum set of parameters (e.g., Transmitter Presets)
- Define the evaluation criteria, such as minimum eye height/width
- Execute and analyze results
Bit error rate (BER) is the ultimate gauge of link performance, but an accurate measure of BER is not possible in relatively short, multi-million-bit simulations.
Instead, this analysis suggests the following pass/fail criteria, which consist of two rules:
- A link must meet the receiver’s eye height (EH) and eye width (EW) requirements
- A link must meet criteria 1 for at least half of Tx Preset settings (≥5 out of 10)
- Criteria 1 establishes that the there is a viable set of settings, which results in the desired BER. The specific EH and EW required by the receiver is implementation-dependent.
- Criteria 2 ensures that the link has adequate margin and is not overly sensitive to the Tx Preset setting.
Use IBIS model and time domain simulations.
We have entered the Age of Artificial Intelligence and Generative AI is developing at a rapid pace and becoming integral to our lives. According to Bank of America analysts, “just as the iPhone led to an explosion in the use of smartphones and phone apps, ChatGPT-like technology is revolutionizing AI”. Generative AI is changing every… Read More »Read More
Data centers today have a lot of servers, and within each server there is an abundance of storage, specialized accelerators, and networking/communications infrastructure. These represent tens of thousands of interconnected systems, and with the rise of hyperscalers and cloud service providers, the scale of data infrastructure is only expected to grow in the years to… Read More »Read More
Interconnect technologies will play an important role in the overall connected car story to meet the needs of mass data transfer within the In-Vehicle Network. We have recently seen these types of challenges and a similar evolution in enterprise data centers, where intelligent systems running data-intensive workloads — such as Artificial Intelligence and Machine Learning — have drastically increased the overall design complexity.Read More
In this PCI-SIG® hosted technical webinar, Astera Labs’ engineers explore the changes between PCIe 4.0 and PCIe 5.0 specifications, including signal integrity and system design challenges, where the right balance must be found between PCB materials, connector types and the use of signal conditioning devices for practical compute topologies. Through an objective analysis, the goal is to provide the audience with a methodology to optimize signal and link integrity performance, present best practices for system board design to support PCIe 5.0 technology applications, and test for system level interoperation.Read More
The upgrade from PCIe® 4.0 to PCIe 5.0 doubles the bandwidth from 16GT/s to 32GT/s but also suffers greater attenuation per unit distance, despite the PCIe 5.0 specification increasing the total insertion loss budget to 36dB. After deducting the loss budget for CPU package, AIC, and CEM connector, merely 16dB system board budget remains. Within the remaining budget, engineers need to consider safety margin for board loss variations due to temperature and humidity.Read More
The design solution space for high-speed serial links is becoming increasingly complex with increasing data rates, diverse channel topologies, and tuning parameters for active components. PCI Express® (PCIe®) 5.0, at 32 GT/s, is a particularly relevant example of an application whose design solution space can be a daunting problem to tackle, given the performance-cost requirements of its end equipment. This paper is intended to help system designers navigate these design challenges by providing a how-to guide for defining, executing, and analyzing system-level simulations, including PCIe 5.0 Root Complex (RC), Retimer, and End Point (EP).Read More
In this PCI-SIG® hosted webinar, Kurt Lender of Intel and Casey Morrison of Astera Labs offer solutions to address signal-integrity and channel insertion loss challenges to ensure the full potential of the increased bandwidth offered by PCIe® Gen 4.0 and 5.0 are achieved.
As PCIe specifications continue to double the transfer rates of previous generations, the technology can address various needs for demanding applications, while signal-integrity and channel insertion loss challenges arise as well. Retimers are mixed-signal analog/digital devices that are protocol-aware and able to fully recover data, extract the embedded clock and retransmit a fresh copy of the data using a clean clock. These devices are fully defined in the PCI Express base specification, including compliance testing, and are used to combat issues that PCI Express faces.Read More
A redriver amplifies a signal, whereas a retimer retransmits a fresh copy of the signal. Retimers provide capabilities such as PCIe® protocol participation, lane-to-lane skew compensation, adaptive EQ, diagnostics features, etc. Therefore, retimers particularly address the need for reach extension in PCIe 4.0 & PCIe 5.0 systems, where increased number of PCIe slots, multiconnectors, and long physical topologies lead to signal integrity (SI) challenges.Read More
PCIe 5.0 ushers in the era of >1Tbps of data bandwidth between two PCIe nodes, and noticeably greater Link Errors and DLLP Retries are likely to occur. By reducing insertion loss (shorter trace, better material, connectors, etc.) or adding retimers to some topologies, system designers can minimize system-level headaches with a target of 1E-17 or lower BER.Read More
Rapidly implement diverse system topologies using our plug-and-play connectivity system boards. Our solutions include:
- CXL Memory Cards: Increase cloud server performance and reduce total cost of ownership through memory expansion, pooling and sharing.
- Smart Cable Modules: Active Copper-Based Solution to Address Reach, Signal Integrity and Bandwidth Utilization Issues for 100G/Lane Ethernet Switch-to-Switch and Switch-to-Server Interconnects.
- Riser Cards: Extend PCIe/CXL technology slots and enable incredibly complex multi-connector topologies.
- PCIe-Over-Cable Extender Cards: Connect a server head-node to a JBoF or JBoG without sacrificing speed.
- GPU Booster Cards: Support external graphics (eGPUs) and enhance the gaming experience.
Rapidly design and achieve signal integrity peace of mind and avoid wondering if a PCIe 4.0/5.0, CXL 1.1/2.0 or 100G/Lane Ethernet technology-based design will work. Our team can help develop first-pass design success and accelerate time to market for your systems and boards.