Leo CXL™ Memory Connectivity Platform
Astera Labs delivers Leo CXL™ Memory Connectivity Platform to eliminate memory bandwidth bottlenecks and capacity constraints for compute-intensive workloads such as AI and ML.
Leo CXL Memory Connectivity Platform is the industry’s first purpose-built solution to support memory expansion, memory pooling and memory sharing using CXL 1.1 and 2.0. Leo includes server-grade customizable Reliability, Availability and Serviceability (RAS), end-to-end security, extensive fleet management capabilities and seamless interoperability with all major CPU, GPU and memory vendors for cloud-scale deployment.
- Purpose-built for cloud scale deployment targeting workloads such as AI and Machine Learning
- Memory expansion, pooling and sharing for heterogeneous CPU/GPU topologies
- CXL Type-3 device supporting CXL 1.1 and 2.0 memory expansion
- CXL interface up to 32 GT/s per lane, up to 16 lanes
- Multiple DDRx channels to increase memory capacity up to 2TB
- Up to 5600 MT/s per memory channel to fully utilize available bandwidth of CXL 1.1 and 2.0 interface
- Server-grade customizable RAS and software APIs to integrate with fleet management services
- Seamless interoperation with all major CPU, GPU, and memory vendors
- Flexible and scalable memory interface with a low-latency data path
- Best-in-class security features to ensure end-to-end data integrity and protection
Leo CXL Memory Connectivity Platform includes a comprehensive portfolio of controllers and hardware solutions:
- Leo E-Series CXL Smart Memory Controller supporting memory expansion
- Leo P-Series CXL Smart Memory Controller supporting memory expansion, pooling, and sharing
- Aurora A-Series Smart Memory Hardware Solutions in add-in-card form factor supporting memory expansion, pooling and sharing
E-Series vs. P-Series
Astera Labs offers two versions of the Leo CXL Memory Connectivity Platform to unlock the benefits of the CXL.mem protocol: the E-Series, which offers memory expansion, and the P-Series, which adds memory sharing and pooling capabilities. Both deliver cloud service providers tools and diagnostics essential for advanced fleet management.

E-Series
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Memory Expansion

P-Series
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Memory Expansion
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Memory Pooling
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Memory Sharing
Aurora A-Series Hardware Solutions
Aurora A-Series CXL Smart Memory Hardware Solutions offer all the benefits of Leo Controllers and enable quick plug-and-play deployment with faster time-to-market for system OEMs and data centers.
- PCIe x16 CEM add-in card form factor
- Lower TCO via more granular serviceability - can replace single failing DIMM
- Configurable memory capacity due to plug-and-play capability of DIMMs
- Up to 4x DDR5 RDIMMs supporting up to 2TB
- On-board debug connectors for fleet management on Cloud Servers
- Temperature and health monitoring of Leo controllers and memory
- RDIMM fault isolation and error correction
- High volume production-qualified solutions with robust supply chain
Why Use Leo CXL Memory Connectivity Platform?
Astera Labs Leo CXL Memory Connectivity Platform is the industry's first purpose-built solution that supports both memory expansion and memory pooling to solve performance bottlenecks and capacity constraints in cloud servers.
Purpose-Built for Cloud
Comprehensive portfolio of purpose-built SoCs and hardware solutions for cloud-scale deployment targeting workloads such as AI and ML
Customizable RAS & Security
Server-grade customizable RAS, end-to-end security features, and software tools to integrate with fleet-management services
Low-Latency DDRx & Custom Memory
Flexible and scalable memory interface with low-latency data path to support JEDEC DDRx and custom memory interfaces
Seamless Interoperability
Seamless interoperability with all major CPU, GPU and memory vendors, making it easy to manage, debug, and deploy at scale
Orderable Information
Leo CXL Smart Memory Controllers
Orderable Part Number | Image | Documents | Description | CXL Spec | CXL Link | Memory | Capacity | Expansion | Pooling / Sharing | Ordering |
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CM5082E-* | ![]() | https://www.asteralabs.com/wp-content/uploads/2022/08/Astera_Labs_Leo_Aurora_Product_FINAL.pdf | Leo E-Series CXL 2.0 x8 Smart Memory Controller | CXL 1.1/2.0 | 8x32G | 2ch DDRx Up To 5600MT/s | 2TB | Yes | No | https://www.asteralabs.com/product-details/cm5082e/ |
CM5162E-* | ![]() | https://www.asteralabs.com/wp-content/uploads/2022/08/Astera_Labs_Leo_Aurora_Product_FINAL.pdf | Leo E-Series CXL 2.0 x16 Smart Memory Controller | CXL 1.1/2.0 | 16x32G | 2ch DDRx Up To 5600MT/s | 2TB | Yes | No | https://www.asteralabs.com/product-details/cm5162e/ |
CM5162P-* | ![]() | https://www.asteralabs.com/wp-content/uploads/2022/08/Astera_Labs_Leo_Aurora_Product_FINAL.pdf | Leo P-Series CXL 2.0 x16 Smart Memory Controller | CXL 1.1/2.0 | 16x32G | 2ch DDRx Up To 5600MT/s | 2TB | Yes | Yes | https://www.asteralabs.com/product-details/cm5162p/ |
Aurora Smart Memory Hardware Solutions
Orderable Part Number | Image | Documents | Description | CXL Spec | CXL Link | Memory | Capacity | Expansion | Pooling / Sharing | Ordering |
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A1000-1P4AA | ![]() | https://www.asteralabs.com/wp-content/uploads/2022/08/Astera_Labs_Leo_Aurora_Product_FINAL.pdf | Aurora A-Series CXL Smart Memory Add-in Card | CXL 1.1/2.0 | 16x32G | 4x DDR5-5600 RDIMM slots | 2TB | Yes | Yes | https://www.asteralabs.com/product-details/aurora-a-series/ |
Evaluation Kits
Orderable Part Number | Image | Documents | Description | CXL Spec | CXL Link | Memory | Capacity | Expansion | Pooling / Sharing | Ordering |
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Leo-SVB-RevA | ![]() | https://www.asteralabs.com/wp-content/uploads/2022/08/Astera_Labs_Leo_Aurora_Product_FINAL.pdf | Leo CXL Smart Memory Controller - System Validation Board | CXL 1.1/2.0 | 16x32G (PCIe CEM) | 4x DDR5-5600 RDIMM slots | 2TB | Yes | Yes | https://www.asteralabs.com/product-details/leo-system-validation-board/ |
Application Notes
Videos

Interop Bulletin 2: Interop Testing with Leo Memory Connectivity Platform and DDR5-5600 RDIMMs
In our Interop Bulletin, we demonstrated interoperability between our Leo CXL Memory Connectivity Platform and DDR5-5600 RDIMMs from Micron, Samsung, and SK hynix.

Demo: Accelerating Database Performance with Leo Memory Connectivity Platform
This video highlights our joint demo with Supermicro and MemVerge at Flash Memory Summit. We showcased a high-performance OLTP (Online Transaction Processing) solution with CXL-attached memory. This collaboration has proven to increase transaction throughput, reduce infrastructure costs and improve user experience for popular services used every day, such as product delivery services, online bookings, online payments, and order tracking and monitoring.
FAQ
CXL™ is needed to overcome CPU-memory and memory-storage bottlenecks faced by computer architects. Future data centers need heterogeneous compute, new memory and storage hierarchy, and an agnostic interconnect to tie it all together. CXL maintains memory coherency between the processor memory space and memory on attached devices to enable pooling and sharing of resources to provide higher performance, reduce software stack complexity, and lower overall system cost.
Traditional DRAM and persistent storage class memory (SCM) are supported, allowing for flexibility between performance and cost.
Compute Express Link™ (CXL™) is an open industry standard interconnect offering high-bandwidth, low-latency connectivity between the host processor and devices including accelerators, memory expansion, and smart I/O devices. CXL utilizes the PCIe® 5.0 physical layer infrastructure and the PCIe alternate protocol to address the demanding needs of high-performance computational workloads in Artificial Intelligence, Machine Learning, communication systems, and HPC through the enablement of coherency and memory semantics across heterogeneous processing and memory systems.
The CXL™ protocol supports three different type of devices:
- Type 1 Caching Devices / Accelerators
- Type 2 Accelerators with Memory
- Type 3 Memory Buffer
- Memory tiering in which additional capacity is applied with a variable mix of lower-latency direct-attached memory and higher-latency large capacity memory
- Higher VM density per system by having more memory capacity attached
- Large databases can use a caching layer provided by SCM to improve the performance
- CXL.io is used for initialization, link-up, device discovery and enumeration, and register access. It provides a non-coherent load/store interface for I/O devices similar to PCIe® 5.0.
- CXL.cache defines interactions between a Host and Device, which allows CXL devices to cache host memory with low latency.
- CXL.mem provides a Host processor with direct access to Device-attached memory using load/store commands.
CXL™ runs on PCIe® 5.0 electrical signals. CXL runs on PCIe PHY and supports x16, x8, and x4 link widths natively.
CXL™ 2.0 adds support for switching, persistent memory, and security as well as memory pooling support to maximize memory utilization, reducing or eliminating the need to over-provision memory.
In traditional servers, memory is directly connected to a specific CPU or GPU (i.e., locked behind the host) and can result in over-provisioning of memory resources when applications are not using the available memory. When the memory is over-provisioned to a specific host, the memory is now stranded and cannot be accessed by other hosts, thereby increasing data center costs. In addition, when memory is locked behind a host, the data being processed by the application needs to be copied through high latency interconnects if a different CPU or GPU needs access to the data.
Memory pooling allows multiple hosts in a heterogenous topology to access a common memory address range with each host being assigned a non-overlapping address range from the “pool” of memory resources. Memory pooling allows system integrators to dynamically allocate memory from this pool, which reduces costs by reducing stranded memory and increasing memory utilization. Memory pooling is part of a growing trend for resource disaggregation or composability for heterogeneous solutions.
Memory sharing allows multiple hosts in a heterogeneous topology to access a common memory address range with each host being assigned the same address range as the other host. This improves memory utilization similar to memory pooling, but also provides an added benefit of data flow efficiency since multiple hosts can access the same data. With memory sharing, coherency needs to be managed between the hosts to ensure data is not overwritten by another host incorrectly.
CXL™ 2.0 supports Integrity and Data Encryption (IDE) and key exchange protocols for to provide end-to-end protection of data on the CXL link.
“RAS” is the ability of the system to provide resilience starting from the underlying hardware all the way to the application software through three components collectively referred to as “RAS” features:
- Reliability: the ability of the system to detect and correct faults
- Availability: how the system guarantees uninterrupted operation with minimal degradation
- Serviceability: the ability of the system to proactively diagnose, repair, upgrade or replace components at scale
Have more questions about general topics, such as PCIe 5.0, ordering, quality, etc.? See the full list of FAQs.
Hardware Solutions
Rapidly implement diverse system topologies using our plug-and-play connectivity system boards. Our solutions include:
- CXL Memory Cards: Increase cloud server performance and reduce total cost of ownership through memory expansion, pooling and sharing.
- Smart Cable Modules: Active Copper-Based Solution to Address Reach, Signal Integrity and Bandwidth Utilization Issues for 100G/Lane Ethernet Switch-to-Switch and Switch-to-Server Interconnects.
- Riser Cards: Extend PCIe/CXL technology slots and enable incredibly complex multi-connector topologies.
- PCIe-Over-Cable Extender Cards: Connect a server head-node to a JBoF or JBoG without sacrificing speed.
- GPU Booster Cards: Support external graphics (eGPUs) and enhance the gaming experience.
Services
Rapidly design and achieve signal integrity peace of mind and avoid wondering if a PCIe 4.0/5.0, CXL 1.1/2.0 or 100G/Lane Ethernet technology-based design will work. Our team can help develop first-pass design success and accelerate time to market for your systems and boards.
Contact us for more information about our design and testing services >