Nov 3, 2021
Enabling Robust CXL™ Connectivity for Intel Sapphire Rapids CPU-based Systems with Synopsys DesignWare CXL Controller IP
In this video, Astera Labs VP of Products Casey Morrison demonstrates the industry’s first fully formed CXL™ link between a root complex, a retimer and end point IP. Specifically, the interoperability demo features an Intel Sapphire Rapids CPU, Astera Labs’ Solstice 3U Riser Card with two Aries CXL Smart Retimers, and the Synopsys DesignWare CXL Controller IP, showing successful transmission of CXL.io, CXL.cache, and CXL.mem transactions.
Industry’s first demonstration of a fully formed CXL™ link between an Intel root complex, an Aries CXL Smart Retimer and Synopsys end point IP.
Learn more about CXL™ Technology
Introduction to Compute Express Link™ (CXL™) Technology
Learn how CXL™ technology enables data centers to achieve higher performance through increased memory capacity and bandwidth at lower latencies.
Ready to find out more?
Contact us for more information about how you can design with confidence and accelerate your time to market.