Smart Cable Modules

Videos

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Aries PCIe®/CXL® Smart Cable Modules™: DesignCon Demo

At DesignCon, we showcased our new Aries PCIe®/CXL® Smart Cable Modules (SCMs) that enable multi-rack GPU clustering for AI with an industry-leading 7-meter reach over flexible copper cables.

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Aries PCIe®/CXL® Smart Cable Modules™: First Look Demo

Get your first look at an end-to-end demonstration of our Aries PCIe/CXL Smart Cable Modules (SCMs) that enable multi-rack GPU clustering for AI with an industry-first 7 meters reach over flexible copper cables.

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Rack-Scale Demo of Taurus Ethernet Smart Cable Modules 

Check out this video demo of our Taurus Ethernet Smart Cable Modules™. Learn about the benefits of Active Electrical Cables and how Taurus enables up to 100G/lane PAM4 for Switch-to-Server and Switch-to-Switch interconnect, at rack scale.

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Taurus Smart Cable Module™ 400GbE PAM4 Connectivity Demonstration

See a Taurus Smart Cable Module™ enabled 400GbE PAM4 Smart Electrical Cable in action with a demonstration of an end-to-end 400GbE link up passing error-free traffic as well as real-time link diagnostics.

Articles & Insights

Cloud Infrastructure Fleet Management Made Easy With COSMOS

Large server deployments for Artificial Intelligence (AI) and general-purpose computing in hyperscale data centers provide enormous benefits in terms of raw compute power, efficiency, and cost amortization. The on-demand nature and low up-front cost of cloud computing is attractive to an increasing number of enterprises. However, managing such a large fleet of systems presents complex… Read More »

Astera Labs’ Flexible CXL Product Suite Enables Low-Latency Memory Expansion

Artificial intelligence (AI) is the single most transformative technology impacting everyday lives. Data-intensive AI applications as well as in-memory databases, high performance computing (HPC) and high-performance file systems are driving the need for faster interconnects between CPUs, GPUs, TPUs, DPUs, SmartNICs and FPGAs. Low latency is also critical, especially for memory interconnects. Compute Express Link™… Read More »

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Breaking Through the Memory Wall

The term “memory wall” was first coined in 1994 to define what was becoming an obvious problem at the time: processor performance was outpacing memory interconnect bandwidth. In other words, memory access was limiting compute performance. Almost 30 years later this statement still holds true, especially in memory-intensive applications such as artificial intelligence (AI) where… Read More »

Astera Labs Delivers Industry-First CXL Interop with DDR5-5600 Memory Modules

Earlier this year, we announced the launch of our Cloud-Scale Interop Lab for CXL to provide robust interoperability testing between our Leo Memory Connectivity Platform and a growing ecosystem of CXL supported CPUs, memory modules and operating systems. By providing this critical testing, we enable customers to deploy CXL-attached memory with confidence by minimizing interoperational… Read More »