In this PCI-SIG® hosted technical webinar, Astera Labs’ engineers explore the changes between PCIe 4.0 and PCIe 5.0 specifications, including signal integrity and system design challenges, where the right balance must be found between PCB materials, connector types and the use of signal conditioning devices for practical compute topologies. Through an objective analysis, the goal is to provide the audience with a methodology to optimize signal and link integrity performance, present best practices for system board design to support PCIe 5.0 technology applications, and test for system level interoperation.
The upgrade from PCIe 4.0 to PCIe 5.0 doubles the bandwidth from 16GT/s to 32GT/s but also suffers greater attenuation per unit distance, despite the PCIe 5.0 specification increasing the total insertion loss budget to 36dB. After deducting the loss budget for CPU package, AIC, and CEM connector, merely 16dB system board budget remains. Within the remaining budget, engineers need to consider safety margin for board loss variations due to temperature and humidity.
Astera Labs explains the signal integrity challenges of PCIe 5.0 and the corresponding OCP system design challenges, where the right balance must be found between PCB materials, connector types, and the use of signal conditioning devices for practical compute topologies: CPU-to-AIC with one/two connectors, JBOG accelerator module baseboard, etc.
Flywheels of Innovation – Astera Labs, AWS, Intel and Six Nines Revolutionizing Semiconductor Development in the Cloud
One of our core values is to innovate exponentially, rather than incrementally, in everything we do. Our innovative 100% cloud-based design approach with partners AWS, Intel and Six Nines is yet another example of how Astera Labs delivers high quality results to our customers on time, meeting spec and within budget. Learn more about our journey in this video produced by AWS and Intel.
Astera Labs Partners with Intel Capital to Accelerate Deployment of Connectivity Solutions for Computation-Intensive Workloads
Jitendra Mohan, Chief Executive Officer of Astera Labs, discusses our collaboration with Intel Capital and continued mission to solve connectivity bottlenecks throughout the data center. Solutions such as our Aries Smart Retimer for PCIe 4.0 and 5.0 are key for our customers to easily design systems that overcome complex performance challenges of intelligent systems.
Interoperability testing of PCIe retimers is critical for HPC and cloud applications. New compute-intensive workloads – such as Artificial Intelligence and Machine Learning – are becoming more mainstream in the enterprise data center, and require an array of high-performance, low-latency devices connected to the PCIe bus that adds to overall system complexity.