Learn how our comprehensive interoperability testing reduces design challenges, so you can accelerate time-to-market, streamline development efforts and reduce costs for designing and deploying heterogeneous infrastructure with CXL technology.
Videos
Astera Labs Video Library
Videos
Interop Testing with CXL 1.1 Host CPU’s and Popular DDR5 Memory Module
After establishing the foundation of our rigorous testing, we worked with our customers to determine the most popular memory configurations for their systems and applications, to which we’ve included in our initial interop reports. We include 64GB DDR5-4800 RDIMMs from Micron, Samsung, and SK Hynix, each of which are tested with CXL 1.1-capable CPUs from AMD and Intel.
Articles & Insights
Astera Labs Joins the Optical Internetworking Forum (OIF) Interoperability Demo at OFC 2023
Partnering with Intel and Supermicro, Astera Labs will demonstrate CXL memory expansion using our industry-leading Leo Smart Memory Controllers running real-world workloads and compare performance benchmarks for direct attach memory vs. CXL attach memory implementation for large in-memory applications. This demonstration will also highlight how our Aries Smart Retimers enable longer PCIe (PCI Express) 5.0 and CXL 1.1. signal reach to implement complex topologies. Both Leo and Aries product lines are in advanced sampling stage and ready for deployment in Cloud servers.
The Importance of Security Features in a CXL Memory Controller to Protect Mission-Critical Cloud Data
The explosion of modern applications such as Artificial Intelligence, Machine Learning and Deep Learning is changing the very nature of computing and transforming businesses. These applications have opened myriad ways for companies to improve their business development processes, operations, and security and to provide better customer experiences. To support these applications, platforms are being designed… Read More »
Deploy Purpose-Built Connectivity Solutions at Scale
Learn how at DesignCon 2023! We are excited to be heading back to DesignCon 2023, taking place January 31-February 2 at the Santa Clara Convention Center. We’ll be demonstrating our portfolio of purpose-built connectivity solutions that eliminate performance bottlenecks throughout the data center. Now, we’re making it easier than ever for you to deploy solutions… Read More »
Top 5 reasons to meet with Astera Labs at Intel® Innovation
Partnering with Intel and Supermicro, Astera Labs will demonstrate CXL memory expansion using our industry-leading Leo Smart Memory Controllers running real-world workloads and compare performance benchmarks for direct attach memory vs. CXL attach memory implementation for large in-memory applications. This demonstration will also highlight how our Aries Smart Retimers enable longer PCIe (PCI Express) 5.0 and CXL 1.1. signal reach to implement complex topologies. Both Leo and Aries product lines are in advanced sampling stage and ready for deployment in Cloud servers.
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