Astera Labs Video Library


Interop Testing with CXL 1.1 Host CPU’s and Popular DDR5 Memory Modules - asteralabs
Interop Testing with CXL 1.1 Host CPU’s and Popular DDR5 Memory Module

After establishing the foundation of our rigorous testing, we worked with our customers to determine the most popular memory configurations for their systems and applications, to which we’ve included in our initial interop reports. We include 64GB DDR5-4800 RDIMMs from Micron, Samsung, and SK Hynix, each of which are tested with CXL 1.1-capable CPUs from AMD and Intel.

Deploy Robust PCIe 5.0 Connectivity wit hAries Smart Retimers
Deploy Robust PCIe® 5.0 Connectivity with Aries Smart Retimers

See our Aries Smart Retimers in action via two interoperability demonstrations with key industry partners’ PCIe® 5.0 root complex and endpoints.

Implement Complex PCIeTopologies with Switches, SRIS Clocking & Aries Smart Retimers
Complex PCIe® Topologies with Switches, SRIS Clocking & Aries Smart Retimers

Learn about PCIe® switches and why certain complex system topologies involving switches need retimers to achieve optimal link performance.

Why We Test

Interoperability testing of PCIe® retimers is critical for HPC and cloud applications to support new compute-intensive workloads – such as Artificial Intelligence (AI) and Machine Learning (ML).

Articles & Insights

PCI Express® 5.0 Architecture Channel Insertion Loss Budget

The upgrade from PCIe® 4.0 to PCIe 5.0 doubles the bandwidth from 16GT/s to 32GT/s but also suffers greater attenuation per unit distance, despite the PCIe 5.0 specification increasing the total insertion loss budget to 36dB. After deducting the loss budget for CPU package, AIC, and CEM connector, merely 16dB system board budget remains. Within the remaining budget, engineers need to consider safety margin for board loss variations due to temperature and humidity.

Retimer to EP segment
Simulating with Retimers for PCIe® 5.0

The design solution space for high-speed serial links is becoming increasingly complex with increasing data rates, diverse channel topologies, and tuning parameters for active components. PCI Express® (PCIe®) 5.0, at 32 GT/s, is a particularly relevant example of an application whose design solution space can be a daunting problem to tackle, given the performance-cost requirements of its end equipment. This paper is intended to help system designers navigate these design challenges by providing a how-to guide for defining, executing, and analyzing system-level simulations, including PCIe 5.0 Root Complex (RC), Retimer, and End Point (EP).

PCIe Retimers to the Rescue Webinar: PCI Express® Specifications Reach Their Full Potential

In this PCI-SIG® hosted webinar, Kurt Lender of Intel and Casey Morrison of Astera Labs offer solutions to address signal-integrity and channel insertion loss challenges to ensure the full potential of the increased bandwidth offered by PCIe® Gen 4.0 and 5.0 are achieved.

As PCIe specifications continue to double the transfer rates of previous generations, the technology can address various needs for demanding applications, while signal-integrity and channel insertion loss challenges arise as well. Retimers are mixed-signal analog/digital devices that are protocol-aware and able to fully recover data, extract the embedded clock and retransmit a fresh copy of the data using a clean clock. These devices are fully defined in the PCI Express base specification, including compliance testing, and are used to combat issues that PCI Express faces.

PCI Express® Retimers vs. Redrivers: An Eye-Popping Difference

A redriver amplifies a signal, whereas a retimer retransmits a fresh copy of the signal. Retimers provide capabilities such as PCIe® protocol participation, lane-to-lane skew compensation, adaptive EQ, diagnostics features, etc. Therefore, retimers particularly address the need for reach extension in PCIe 4.0 & PCIe 5.0 systems, where increased number of PCIe slots, multiconnectors, and long physical topologies lead to signal integrity (SI) challenges.