Learn how our comprehensive interoperability testing reduces design challenges, so you can accelerate time-to-market, streamline development efforts and reduce costs for designing and deploying heterogeneous infrastructure with CXL technology.
Videos
Astera Labs Video Library
Videos
Interop Testing with CXL 1.1 Host CPU’s and Popular DDR5 Memory Module
After establishing the foundation of our rigorous testing, we worked with our customers to determine the most popular memory configurations for their systems and applications, to which we’ve included in our initial interop reports. We include 64GB DDR5-4800 RDIMMs from Micron, Samsung, and SK Hynix, each of which are tested with CXL 1.1-capable CPUs from AMD and Intel.
Articles & Insights
3 Key Takeaways from the Optical Fiber Communications (OFC) Conference and Expo
Earlier this month, Astera Labs participated in the largest-ever multi-vendor interoperability demo hosted by the Optical Internetworking Forum (OIF) where more than 30 member companies came together to showcase next-generation control management, electrical, and optical technologies. At the show, Astera Labs demonstrated compliance of its Taurus Ethernet Smart Cable Modules™ (SCM) with the OIF’s Common… Read More »
Let’s Get Real with CXL at MemCon!
Join us at this industry-first memory event focused on end users and systems, taking place Tuesday March 28 through Wednesday March 29 at the Computer History Museum in Mountain View, California. In today’s data centers, the exponential growth in Artificial Intelligence and Machine Learning applications is driving the need for a significant increase in memory…. Read More »
Cloud-Scale Infrastructure Fleet Management Made Easy with Aries Smart Retimers
Data centers today have a lot of servers, and within each server there is an abundance of storage, specialized accelerators, and networking/communications infrastructure. These represent tens of thousands of interconnected systems, and with the rise of hyperscalers and cloud service providers, the scale of data infrastructure is only expected to grow in the years to… Read More »
Astera Labs Joins the Optical Internetworking Forum (OIF) Interoperability Demo at OFC 2023
Partnering with Intel and Supermicro, Astera Labs will demonstrate CXL memory expansion using our industry-leading Leo Smart Memory Controllers running real-world workloads and compare performance benchmarks for direct attach memory vs. CXL attach memory implementation for large in-memory applications. This demonstration will also highlight how our Aries Smart Retimers enable longer PCIe (PCI Express) 5.0 and CXL 1.1. signal reach to implement complex topologies. Both Leo and Aries product lines are in advanced sampling stage and ready for deployment in Cloud servers.