Dec 8, 2020
Interop Bulletin #3 explores the topic of PCIe® switches and reviews why certain complex system topologies involving switches need retimers to achieve optimal link performance.
Specifically, we demonstrate how Aries PCIe Smart Retimers support SRIS to ensure proper PCIe 4.0 data speeds in a scenario that includes a CPU to a retimer card to a switch within a JBOF.
Learn about PCIe® switches and why certain complex system topologies involving switches need retimers to achieve optimal link performance.
Related Links
Learn more about Cloud-Scale Interop Testing
Interop Bulletin: Astera Labs Completes Interop Testing with 5th Gen Intel Xeon Scalable Processors
We’ve collaborated with Intel to offer our portfolio of PCIe® and CXL® solutions to unleash the full potential of 5th Gen Intel Xeon Scalable processors. We have completed rigorous interoperability testing in our Cloud-Scale Interop Lab to enable hyperscalers and OEMs to mitigate design risks, accelerate time-to-market, and deploy Intel-based platforms with confidence at cloud-scale.
Interop Bulletin 2: Interop Testing with Leo CXL Smart Memory Controllers and DDR5-5600 RDIMMs
In our Interop Bulletin, we demonstrated interoperability between our Leo CXL Memory Connectivity Platform and DDR5-5600 RDIMMs from Micron, Samsung, and SK hynix.
Demo: Accelerating Database Performance with Leo CXL Smart Memory Controllers
This video highlights our joint demo with Supermicro and MemVerge at Flash Memory Summit. We showcased a high-performance OLTP (Online Transaction Processing) solution with CXL-attached memory. This collaboration has proven to increase transaction throughput, reduce infrastructure costs and improve user experience for popular services used every day, such as product delivery services, online bookings, online payments, and order tracking and monitoring.
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