Learn how at DesignCon 2023!
We are excited to be heading back to DesignCon 2023, taking place January 31-February 2 at the Santa Clara Convention Center. We’ll be demonstrating our portfolio of purpose-built connectivity solutions that eliminate performance bottlenecks throughout the data center.
Now, we’re making it easier than ever for you to deploy solutions at scale! Learn how:
- Our Smart Silicon Products with a rich set of diagnostics and fleet management capabilities simplify deployment and effectively manage solutions at scale.
- Our Easy-to-Use System-Level Solutions enable plug-and-play operation today.
- Our Cloud-Scale Interop Lab ensures seamless interoperability to deploy with confidence.
Can’t Miss Technology Demonstrations
Visit Astera Labs in Booth #854 to learn how our silicon, software, and system-level solutions help customers realize the vision of Artificial Intelligence and Machine Learning in the Cloud through CXL™, PCIe®, and Ethernet technologies.
- Taurus Ethernet Smart Cable Modules™ remove rack-level Ethernet bottlenecks with thin and flexible cables that provide reach extension up to three meters. This live demo shows how Taurus is ready to enable up to 100G/lane PAM4 for Switch-to-Server and Switch-to-Switch interconnects—at rack scale. Learn how our solutions provide all the benefits of general-purpose Active Electrical Cables while enabling a flexible cable supply chain with multiple cable vendors and offering fleet-wide manageability for cloud-scale deployments.
- Aries PCIe/CXL Smart Retimers extend reach and enable complex topologies in data-centric systems. Aries Smart Retimers are the most widely deployed in the industry and have been validated for interoperability with all major root complexes and endpoints. This demo on an AMD platform shows how Aries enables robust PCIe 5.0 connectivity in a complex system. Learn how our solutions reduce design efforts with Astera’s automated loop tests and accelerate system deployment with advanced diagnostics capabilities.
- Leo Memory Connectivity Platform removes processor memory bottlenecks and capacity limitations to increase performance and reduce TCO. In partnership with Lenovo and Intel, we will demonstrate CXL memory expansion, running an in-memory database application on CXL-attached memory. Learn about the comprehensive set of APIs offered through the Leo C-SDK Layer for cloud-scale fleet management and diagnostics.
Can’t Miss Presentations
Our experts will be on stage at DesignCon; join us to learn more about the breakthrough CXL memory coherent standard that is enabling data-intensive workloads in heterogeneous compute architectures. We’ll also share details of the OIF’s work on co-packaging of optical and electrical interfaces.
- Richard Ward, Chief Technologist for Data Connectivity, will join other OIF experts as a panelist to discuss Enabling Next Generation Co-Packaging Solutions on January 31 from 4:45pm-6:00pm in Ballroom D.
- Sandeep Dattaprasad, Senior Product Manager, will present on End-to-End Security Features Protecting Mission-Critical Data for CXL-based Platforms on February 1 from 11:15am-12:00pm in Ballroom E. In this session, Sandeep will:
- Provide insight into the various security threats that can target a CXL-based platform
- Outline security mechanisms that provide confidentiality and integrity for data transiting the CXL Link, and describe industry best-practices to protect data in transit, data in use and data at rest
- Describe industry-leading cryptography schemes that Leo Memory Connectivity Platform supports to enable confidential compute and protect mission critical data in cloud servers
- Ahmad Danesh, Associate Vice President of Product Management, will join the panel discussion Compute Express Link 3.0: Enabling New Usage Models in Composable Disaggregated Infrastructure on February 1 from 4:00pm-5:15pm in Ballroom D.
Schedule a Meeting Today
Click here to schedule a meeting with our memory and data connectivity experts at DesignCon. We hope to see you at the show!