Leo Interop

Deploy CXL-attached memory at scale with confidence

Rigorous testing of Leo Memory Controllers with industry-leading hosts, memory, and operating systems
Comprehensive testing including PCIe electrical, memory, CXL® compliance and system level for end-to-end coverage
Extensive testing with COSMOS software suite for Link, Fleet and RAS telemetry and diagnostics

Interop Bulletins

Michael on Leo Memory Connectivity Platform First Look Demo

Interop Testing with Linux Operating Systems and Leo

Learn how Astera Labs is enabling the CXL ecosystem with software support to support disaggregated memory architectures.

Leo CXL Memory Controller with Intel Xeon 6 – In-Memory Database Performance

Leo Interop with Intel Xeon 6 Processors

Astera Labs has completed successful interop testing between Leo CXL Smart Memory Controllers and Intel Xeon 6 Processors.

DDR5 5600 Memory Architecture Diagram – Leo CXL Memory Controller Compatibility

Interop Testing with Leo and DDR5-5600 RDIMMs

Learn about industry-first interoperability testing between Leo and DDR5-5600 RDIMMs from Micron, Samsung, and SK hynix.

Leo CXL Interop Bulletin 2 – Astera Labs Engineer Presenting Demo

Interop Testing with CXL® 1.1 Host CPUs & DDR5 Memory

Learn about interop testing with 64GB DDR5 RDIMMs from Micron, Samsung, and SK Hynix, each of which are tested with CXL® 1.1-capable CPUs from AMD and…

Example Tests

CXL® Compliance Tests

PCIe Electrical Testing
Transaction Layer Testing
Arbitrator and Multiplexer
Power Management Tests
Reset and Initialization Tests

System & Memory Tests

DDR Tests
Stress Tests
Traffic Tests
Security Tests
Reliability, Availability, and Serviceability