OCP Global Summit 2026

Visit Astera Labs at the San Jose Convention Center, Booth B34
October 12-15

AI Your Way. Any Workload, Any Accelerator, Any Architecture.

Featured Event: Executive Session

AI Your Way: Compute Agnostic, Rack-Scale Architecture for AI Factories

Chris Petersen, Vice President and Technologist, Office of the CTO

Monday, Oct. 12, 12:25-12:45 PM
Lower Level, LL21BC

Join Us for Happy Hour

Wednesday, October 14 | 3:00-5:00 PM, Astera Labs Booth B34

Join us in our booth for drinks, bites, music, and networking.

See the Demos

Experience AI Your Way with live demos and a full showcase of our rack-scale AI connectivity portfolio.

  • Rack-Scale Infrastructure for Any Accelerator – GPU-agnostic architecture for ready-to-deploy inference capacity
  • Memory Wall Solved for Agentic AI – Fabric-attached, CPU-attached, memory expansion, and memory pooling solutions
  • Copper and Optical Signal Conditioning – Connectivity within and beyond the rack at next-gen AI data rates

Speaker Schedule

Watch our experts discuss how the right infrastructure drives performant, token-efficient AI across increasingly specialized workloads.

Bring Your Own XPU: An Open Rack for Inference Performance and TCO

Chris Petersen
Vice President and Technologist, Office of the CTO

Tuesday, October 13, 1:00-1:20 PM
Concourse Level, 220B

Architecting Openness: How Switches Enable the Future of Open Adapter Card Platforms

Chris Blackburn
Director, Solutions Architecture

Wednesday, October 14, 10:05-10:20 AM
Lower Level, LL21BC

Light on the Horizon: Architecting Scale Up Fabrics with NPO & CPO for the Next Gen Data Center

Chris Blackburn
Director, Solutions Architecture

Jignesh Shah
Senior Director of Product Marketing, Signal Connectivity Group

Wednesday, October 14, 10:45-11:00 AM
Concourse Level, 210AE

From Fragmentation to Footprint: The OCP Standard for AI Signal Conditioners

Casey Morrison
Chief Product Officer

Liang Xue
VP, Advanced Hardware Engineering

Wednesday, October 14, 11:15-11:30 AM
Lower Level, LL21BC

Powering AI at Scale: Inside the UALink Ecosystem (UALink Panel)

Helia Naeimi
Senior Director of Technology

Wednesday, October 14, 12:30-12:55 PM
Concourse Level, 220B

Cost-Efficient LLM Inference via Peer-to-Peer GPU-to-Memory Expansion Datapath

Amit Golander, PhD
Memory & Storage Associate Vice President

Moshe Twitto
Fellow, Silicon Engineering

Thursday, October 15, 9:10-9:30 AM
Lower Level, LL21BC

From Securing Links to Securing Pods: Security of Scale-Up Networks

Avdhesh Chhodavdia
Technologist

Thursday, October 15, 1:35-1:50 PM
Concourse Level, 212

From Training to Tokens: Revolutionizing AI Inference with In-Network Compute

Caleb Shetland
Senior Principal Firmware Architect

Helia Naeimi
Senior Director of Technology

Thursday, October 15, 3:10-3:30 PM
Concourse Level, 220B

Technology Insights

Technology Insights