We’ve been framing the increasing adoption of optical connectivity for scale-up applications with a clear organizing principle: Copper where you can, optics where you must. At today’s per-lane signaling rates in rack-scale AI fabrics, “must” is moving inside the rack. The reach and loss budgets available to passive copper compress with every protocol generation, and a growing number of links — even within the scale-up domain — are running into physical limits copper cannot solve with more lanes or better equalization.
Co-packaged optics (CPO) has emerged as the industry’s long-term target precisely because it offers the highest potential radix and the largest power savings relative to pluggable or near-package optics (NPO) architectures. But moving from a discrete pluggable module to an optical engine sitting directly on a chip package raises a new question: How do you actually connect an optical fiber to that package with the performance, manufacturability, and serviceability rack-scale AI demands?
This blog surveys the major optical fiber-to-chip connector technology families in development, the manufacturing processes behind them, and performance and manufacturability tradeoffs that matter most when choosing the right connector for rack-scale AI.
What Is an Optical Fiber-to-Chip Connector?
In CPO architectures, an optical fiber-to-chip connector is the detachable interface between an optical fiber and a photonic integrated circuit (PIC). This connector couples light from a fiber, or a fiber array, into and out of the waveguides built into the PIC. The detachability facilitates system assembly and serviceability. Historically, the detachable fiber interface has lived at the edge of a pluggable transceiver module mounted at the front panel of a switch or server, well removed from the ASIC or switch silicon it serves.
Rack-scale AI signaling is compressing that distance toward zero. As NPO and CPO architectures move the optical engine off the front panel and adjacent to or onto the compute or switch package, the fiber-to-chip interface has to migrate with it. And as part of this migration, it must shrink from a rack-unit-scale connector into a component that fits within the mechanical envelope of a chip package and can survive the assembly and rework processes used in semiconductor package manufacturing besides fulfilling the usual thermal cycling and mechanical shock reliability requirements.
Moving the optical interface onto the semiconductor package reduces system-level power consumption by eliminating the electrical reach a signal must travel before conversion to light. But it also introduces substantial new challenges for precision assembly, field serviceability, long-term reliability, yields, and manufacturing scalability that simply didn’t exist or had been solved for optical interfaces on the front panel.
Why Are Optical Connectors Important for AI Scale-Up?
Co-packaged optics is a design goal for scale-up interconnects because every microsecond of added latency between accelerators that sit within the same compute node or the same coherent memory domain and every watt of power overhead directly erode the efficiency of tightly synchronized collective operations. Scale-up fabrics prioritize interconnect hardware with the highest radix possible. A large number of individual fiber connections must thus exit a single package in order to support the dense multi-path accelerator fabrics and the high data rates modern AI workloads require.
The best-suited optical fiber-to-chip connector technologies for AI scale-up are the ones that can pack the greatest possible number of fibers into the smallest possible footprint along the edge of a package, a metric referred to as “shoreline density.” A connector that enables high shoreline density lets architects maximize the optical lane count attached to a given package edge without expanding the package itself.
Types of Optical Fiber-to-Chip Connectors
The micro-optics required for NPO and CPO fiber-to-chip connectors can be broadly divided into glass and silicon technologies. Across these material families there exist multiple distinct fabrication approaches, and each combination of material and process carries its own profile of precision, repeatability, density, and manufacturing cost. Understanding these tradeoffs is essential to understanding why the industry hasn’t yet converged on a single dominant connector architecture.
Glass Micro-Optics: Selective Laser Etching
One approach to producing glass micro-optics for optical fiber-to-chip connectors relies on a subtractive, laser-based writing process. Glass is exposed to a high-power pulsed laser that is precisely focused to write a desired structure into it, modifying the glass network’s microstructure. That modification changes how the glass responds to a subsequent wet-etch step: When the substrate is placed in an etching agent such as hydrofluoric acid, the laser-modified regions etch away far faster than the surrounding unmodified glass, revealing the desired optical structure.
Because the laser must expose the glass point by point to build a complete three-dimensional structure, this technique is closer to a point-by-point 3D writing process than batch manufacturing. Components are fabricated individually rather than produced in large numbers within a single cycle, constraining throughput at volume and introducing part-to-part variability, since each structure is written independently rather than replicated from a shared master form. That variability makes tight quality control harder to sustain across a large production run.
Glass Micro-Optics: Isothermal Glass Molding
A second glass fabrication approach relies on precision glass molding (PGM) rather than direct writing. The engineering effort is front-loaded into producing a highly accurate mold; once that mold exists, the molding process itself is highly repeatable, and a single production cycle can replicate many finished components simultaneously rather than one at a time. Because every part in a batch is formed from the same master geometry, dimensional consistency across parts is markedly higher than with a serial, point-by-point process like selective laser etching. Quality control is simplified and the manufacturing process scales more readily. Moreover, parts are manufactured in parallel by molding them side-by-side into glass panels, offsetting the time needed for the thermal cycles that are part of the isothermal glass molding process.
This process also enables molding of extremely complex geometries within a single monolithic piece, while other approaches like the ones covered below rely on the bonding of multiple parts.
Silicon Micro-Optics: CMOS-Derived Lens Placement and Grayscale Lithography
On the silicon side, micro-lens-array fabrication can leverage substrates and process infrastructure originally developed for CMOS manufacturing. This heritage gives silicon-based micro-optics a distinct advantage in terms of manufacturing scalability: wafers of sizes up to 300 mm, much larger than those used today in glass molding processes. The placement of the lenses in this approach can also achieve nanometer-scale precision owing to the mature CMOS processes used.
Forming the lens elements on a silicon substrate typically relies on thermal reflow of the resist or on grayscale lithography, which modulates exposure dose across a lens area to sculpt curved surfaces into the resist, whose shape is later transferred into the silicon with a dry etching process. While placement is extremely precise, the curvature this technique produces is less repeatable, so the radius of curvature can vary from lens to lens and device to device. This manufacturing method also limits the fill factor of the lenses: They cannot be as closely packed as molded lenses, which limits achievable shoreline density. The environmental control requirements for grayscale lithography in a semiconductor clean room also add to the overall cost of the process. Due to limitations in the shapes that can be manufactured, silicon micro-optics are often assembled with further components to complement their functionality.
Discrete Micro-Optic Assembly
This approach builds the fiber-side interface from multiple discrete parts rather than a single molded piece: a separate lens array bonded to a separate prism, for instance. These individual parts are simpler to fabricate than complex monolithic micro-optics.
However, because these components aren’t formed as a single unit, they must be aligned and bonded together, adding an assembly step relative to a monolithic design. Adhesives sitting directly in the optical signal path constrain the optical power that can pass through the system or must be replaced by advanced bonding techniques.
Fiber Attachment and Termination
In some approaches, de-ribbonized fiber arrays are cleaved with a CO2 laser. This process depends on holding cleave position within a few microns across every fiber, which is difficult to guarantee repeatably at volume.
By contrast, terminating fibers in a conventionally polished fiber array unit, a well-established technology with decades of manufacturing history, offers a more repeatable alternative with components that are easily sourced in the existing ecosystem.
Some approaches also rely on multiple reflections between the PIC- and fiber-sided micro-optics to increase alignment tolerances beyond what can be achieved with a direct transmission. This results in a trade-off between the alignment tolerance that must be guaranteed by the receptacle and the retention mechanism holding the two together and the complexity of the micro-optics.
A Converging Package-Edge Connector Ecosystem for the AI Scale-Up Optical Roadmap
Design engineers will weigh each of the trade-offs resulting from the choice of material and fabrication approach as they build out their BOMs for tomorrow’s co-packaged optical solutions and gravitate towards a specific connector technology. One single connector technology surveyed here wins outright across almost every axis that matters for rack-scale AI: Isothermal glass molding differentiates itself through shoreline density, manufacturing repeatability and power handling at a highly competitive cost point.
As the “must” in “optics when you must” increasingly points into the scale-up domain, the optical connector ecosystem will play a large role in determining how efficiently the industry can deliver higher radix and lower power via CPO. For a deeper look at the forces driving adoption of optical connectivity, read our companion piece on the five factors influencing decisions along the copper-optical continuum.