Aries Interop

Extending interoperability leadership with PCIe® 6.x testing

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Enabling Seamless Plug-and-Play Interoperability

Reduce design challenges and accelerate time-to-market for AI servers and racks

  • Rigorous testing of Aries Retimers with all major root complexes and 50+ endpoints
  • PCIe® robustness validated with varying channel insertion loss budgets in chip-to-chip, box-to-box, and rack-to-rack topologies
  • Extensive testing with software suite for advanced Link, Fleet, and RAS telemetry and diagnostics
  • Cloud-Scale Interop Lab expands to Taiwan to facilitate closer collaboration with ODMs and accelerate AI platform deployments

 

Why We Test

Extensive testing is required to ensure robust interoperability between the wide variety of PCIe 6.x components within an AI system deployed at cloud-scale.

How We Test

We test Aries Smart DSP Retimers with a broad variety of hosts and end points interconnected over varying channel insertion loss budgets in real systems over thousands of iterations.

Interop Bulletins

Systems and Test Suites Dedicated to Interop

Example Tests

PCIe® Loop Tests

  • Secondary Bus Reset
  • Forward Error Correct (FEC)
  • Link Retrain
  • EQ Redo
  • Speed Change
  • L1 PM
  • Warm Reboot
  • Low-power state (L0p)
  • Flow Control Unit (Flit)

Additional Tests

  • Hot Unplug/Plug
  • Power Cycle Tests
  • Lane Margining
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