Dec 8, 2020
Interop Bulletin #3 explores the topic of PCIe® switches and reviews why certain complex system topologies involving switches need retimers to achieve optimal link performance.
Specifically, we demonstrate how Aries PCIe Smart Retimers support SRIS to ensure proper PCIe 4.0 data speeds in a scenario that includes a CPU to a retimer card to a switch within a JBOF.
Learn about PCIe® switches and why certain complex system topologies involving switches need retimers to achieve optimal link performance.
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How We Test: Leo Memory Connectivity Platform
Learn how our comprehensive interoperability testing reduces design challenges, so you can accelerate time-to-market, streamline development efforts and reduce costs for designing and deploying heterogeneous infrastructure with CXL technology.
Interop Testing with CXL 1.1 Host CPU’s and Popular DDR5 Memory Module
After establishing the foundation of our rigorous testing, we worked with our customers to determine the most popular memory configurations for their systems and applications, to which we’ve included in our initial interop reports. We include 64GB DDR5-4800 RDIMMs from Micron, Samsung, and SK Hynix, each of which are tested with CXL 1.1-capable CPUs from AMD and Intel.
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