Reduce TCO by optimizing memory resource utilization
Orderable Part Number | Image | Documents | Description | CXL Spec | CXL Link | Memory | Capacity | Expansion | Pooling / Sharing | Ordering |
---|---|---|---|---|---|---|---|---|---|---|
CM5162P-* | ![]() | https://www.asteralabs.com/wp-content/uploads/2022/08/Astera_Labs_Leo_Aurora_Product_FINAL.pdf | Leo P-Series CXL 2.0 x16 Smart Memory Controller | CXL 1.1/2.0 | 16x32G | 2ch DDRx Up To 5600MT/s | 2TB | Yes | Yes | https://www.asteralabs.com/product-details/cm5162p/ |
A1000-1P4AA | ![]() | https://www.asteralabs.com/wp-content/uploads/2022/08/Astera_Labs_Leo_Aurora_Product_FINAL.pdf | Aurora A-Series CXL Smart Memory Add-in Card | CXL 1.1/2.0 | 16x32G | 4x DDR5-5600 RDIMM slots | 2TB | Yes | Yes | https://www.asteralabs.com/product-details/aurora-a-series/ |
Leo-SVB-RevA | ![]() | https://www.asteralabs.com/wp-content/uploads/2022/08/Astera_Labs_Leo_Aurora_Product_FINAL.pdf | Leo CXL Smart Memory Controller - System Validation Board | CXL 1.1/2.0 | 16x32G (PCIe CEM) | 4x DDR5-5600 RDIMM slots | 2TB | Yes | Yes | https://www.asteralabs.com/product-details/leo-system-validation-board/ |