Cable Extender Cards
Enabling Out-of-the-Box PCIe® Expansion
RT = Retimer
Requirements & Challenges
- Cable, connector, and total board losses on both sides of the link make retiming a requirement for PCIe® 4.0 and PCIe 5.0 implementations
- SRIS/SRNS topologies are preferred because providing copies of REFCLK across each cable adds EMI challenges and additional cost
Aries Retimer Benefits
- Supports separate reference clock (SRNS/SRIS) to accommodate out-of-box PCIe interconnect without needing to send REFCLK across the cable
- Retimers can be cascaded for cases with very long cables or large / difficult tray layouts (retimers located both on server and JBoF/JBoG)
- Deep diagnostic features supported in BMC-tested SDK
Products
Product | Documents | Description | Max PCIe Gen | PCIe Lanes | Ordering |
Astera Labs PCIe® 4.0, PCIe 5.0, and CXL™ x16 and x8 Low-Latency Smart Retimers | PCIe 5.0 | x 8 |