Discover how Active Cable Backplane technology is redefining copper connectivity for rack-scale AI infrastructure—enabling higher density, extended reach, and lower power as systems scale beyond 72+ accelerators.
Dive into the challenges of modern AI server design and explore use case examples of how Scorpio P-Series Fabric Switches overcome these obstacles.
Learn how the Scorpio Smart Fabric Switch Portfolio optimizes AI dataflows with reliable connectivity and scalability, now ready for next-gen deployments.
Learn how our COnnectivity System Management and Optimization Software (COSMOS) enables at-scale monitoring and resource optimization.
This application notes describes how to complete a hardware product design using Leo CXL® Smart Memory Controllers.
This application note provides an overview of the Leo firmware and software structure, operation, usage and configuration. Interactions during the system boot sequence and CXL® link configuration are also covered.
Ensuring your design is done right the first time is top priority. This checklist will help to verify schematics follow Astera Labs’ recommended guidelines.
This guide provides an overview of Leo’s best-in-class security features aligned with industry specifications to ensure device and firmware integrity for trusted cloud deployment.
This application note provides an overview of Leo’s error correction, and Reliability, Availability and Serviceability (RAS) feaures supported by the memory subsystem, CXL® subsystem and application layer.
Learn how to use our built-in self-test feature for diagnosing situations where a device is suspected to be damaged or non-functional.
Learn how to use our Aries Smart Retimer and associated C-SDK collateral in a system where security and robustness are critical for maximizing system performance and up-time.
Learn how Aries supports lane margining for both timing and voltage, including an example with the Intel Lane Margining Tool (LMT).
Learn how to use our Python-SDK to automatically sweep over all Transmitter preset settings to capture the bit error rate (BER), margin information, and more in a loopback configuration.
Learn how to use Aries’ built-in pseudo-random bit sequence (PRBS) pattern generators and checkers to perform physical-layer stress tests and monitor per-lane margins and bit error rate.
Learn how to use the Aries plug-in for CScripts to automate system-level tests of PCIe® Links in an Intel-based system.