Now you can design with confidence. At Astera Labs, we understand that standards compliance and plug-and-play interoperability is critical for our customers. For this reason, we rigorously test our products like Aries Smart Retimer portfolio for interoperability with all major root complexes and PCI Express® (PCIe®) endpoints — making it the most widely tested PCIe 4.0 and PCIe 5.0 retimer solution on the market. It is the high standard our customers demand, and we are proud to deliver it.
Interop Bulletins
Get the latest updates from our Interop engineering team on the devices and use cases guiding our testing operations.
Deploy Robust PCIe® 5.0 Connectivity with Aries Smart Retimers
See our Aries Smart Retimers in action via two interoperability demonstrations with key industry partners’ PCIe® 5.0 root complex and endpoints.
Complex PCIe® Topologies with Switches, SRIS Clocking & Aries Smart Retimers
Learn about PCIe® switches and why certain complex system topologies involving switches need retimers to achieve optimal link performance.
Why We Test
Interoperability testing of PCIe retimers is critical for HPC and cloud applications. New compute-intensive workloads – such as Artificial Intelligence and Machine Learning – are becoming more mainstream in the enterprise data center, and require an array of high-performance, low-latency devices connected to the PCIe bus that adds to overall system complexity.
How We Test
Aries Smart Retimers are rigorously tested with all major root complexes and an ever-increasing range of PCIe endpoints to ensure seamless interoperation and low-risk designs. Each device is put through our exhaustive testing regime that uses the latest PCIe 4.0 systems from Intel and AMD to exercise the PCIe link to the target endpoint with a battery of tests over thousands of iterations.
Design with Confidence
The Cloud-Scale Interop Lab testing process establishes interoperability between Astera Labs Retimers and an exhaustive sampling of PCIe devices, allowing you to design with confidence, and reduce your development time and effort.
Endpoints / Root Complex Devices Tested
Example Tests
Intel PCIe Loop Tests
- Secondary Bus Reset
- Link Disable/Enable
- Link Retrain
- EQ Redo
- Speed Change
- L1 PM
- Warm Reboot
AMD System Deck Loop Tests
- Secondary Bus Reset
- Link Disable/Enable
- EQ Redo
- Speed Change
Other Tests
- Hot Unplug/Plug
- Power Cycle Tests
- Lane Margining
Customizable Testing Services
Astera Labs offers tailored performance and interoperability testing services to address each of our partners’ specific PCIe retimer integration needs. Contact us to learn more about our customizable testing services.