Jun 9, 2020
This presentation explores the signal integrity challenges of PCIe® 5.0 and the corresponding OCP system design challenges, where the right balance must be found between PCB materials, connector types, and the use of signal conditioning devices for practical compute topologies: CPU-to-AIC with one/two connectors, JBOG accelerator module baseboard, etc.
Each topology has multiple factors impacting SI—package, channel insertion/reflection loss, and crosstalk—requiring tradeoffs between physical channel length, interconnect solution, PCB design/material, etc.
Through an objective analysis using open-source tools, the goal is to provide the audience with a step-by-step methodology to optimize their topology between low-loss PCB material, alternative connectors, signal retimers, or some combination thereof. Finally, to improve link uptime and maximize the potential of PCIe 5.0 throughput and latency, we explore the relationship between Lane BER and Link stability.
Event: OCP Virtual Summit 2020
Speakers: Casey Morrison & Pulkit Khandelwal
Astera Labs explains the signal integrity challenges of PCIe® 5.0 and the corresponding OCP system design challenges, where the right balance must be found between PCB materials, connector types, and the use of signal conditioning devices for practical compute topologies.
Related Links
Learn more about PCIe 5.0
Intel Vision 2022
Check out this demo video from Intel Vision featuring our Aries PCIe® Smart Retimers enabling robust PCIe 5.0 connectivity with KIOXIA America, Inc. SSDs and Intel Corporation’s Sapphire Rapids CPU.
Intel Innovation 2021: Astera Labs, Broadcom, Intel & Samsung PCI Express® 5.0 Demo
Astera Labs joined Broadcom, Intel, and Samsung at Intel Innovation 2021 to demonstrate seamless end-to-end PCI Express® (PCIe®) 5.0 interoperation at 32GT/s.
Ready to find out more?
Contact us for more information about how you can design with confidence and accelerate your time to market.