Blog

Home > Resources

PCIe Retimers to the Rescue Webinar: PCI Express® Specifications Reach Their Full Potential

by

In this PCI-SIG® hosted webinar, Kurt Lender of Intel and Casey Morrison of Astera Labs offer solutions to address signal-integrity and channel insertion loss challenges to ensure the full potential of the increased bandwidth offered by PCIe® Gen 4.0 and 5.0 are achieved.

As PCIe specifications continue to double the transfer rates of previous generations, the technology can address various needs for demanding applications, while signal-integrity and channel insertion loss challenges arise as well. Retimers are mixed-signal analog/digital devices that are protocol-aware and able to fully recover data, extract the embedded clock and retransmit a fresh copy of the data using a clean clock. These devices are fully defined in the PCI Express base specification, including compliance testing, and are used to combat issues that PCI Express faces.

PCI Express Retimers vs. Redrivers: An Eye-Popping Difference

by

Retimers and Redrivers have enabled longer physical channels in servers and storage systems since Peripheral Component Interface Express (PCIe®) 3.0 was first introduced almost 10 years ago. Now that PCIe 4.0 is ramping up and PCIe 5.0 is just around the corner, how do these reach extension tools stack up in the face of new challenges in high-speed connectivity?

This article explains the differences between Retimers and Redrivers in IC block diagram, capabilities and use cases.

The impact of Bit Errors in PCI Express Links: The Painful Realities of Low-Probability Events

by

Retimers and Redrivers have enabled longer physical channels in servers and storage systems since Peripheral Component Interface Express (PCIe®) 3.0 was first introduced almost 10 years ago. Now that PCIe 4.0 is ramping up and PCIe 5.0 is just around the corner, how do these reach extension tools stack up in the face of new challenges in high-speed connectivity?

This article explains the differences between Retimers and Redrivers in IC block diagram, capabilities and use cases.

Why We Test

by

Interoperability testing of PCIe retimers is critical for HPC and cloud applications. New compute-intensive workloads – such as Artificial Intelligence and Machine Learning – are becoming more mainstream in the enterprise data center, and require an array of high-performance, low-latency devices connected to the PCIe bus that adds to overall system complexity.

Categories

Archives