Oct 20, 2019
Presented by Astera Labs for PCI-SIG
In this video, Casey Morrison gives a quick tutorial on PCIe® Retimers – What do they do? When to use them? What key features to look for? PCI-SIG® compliance requirements, etc.
Signal-integrity challenges will be significant in PCIe 4.0 and PCIe 5.0 due to increased data rates. A PCIe Retimer is a cost-optimized option to provide more margins and enable a robust link. Compliance tests meeting electrical and protocol specifications, latency, small total footprint, power consumption, bifurcation capacity, in-band and side-band diagnostics are key features system designers should look for in Retimers.
Quick tutorial on PCIe® Retimers — What do they do? When to use a retimer? What key features to look for? PCI-SIG compliance requirements and more!
Learn more about PCIe Retimers
Intel Vision 2022
Check out this demo video from Intel Vision featuring our Aries PCIe® Smart Retimers enabling robust PCIe 5.0 connectivity with KIOXIA America, Inc. SSDs and Intel Corporation’s Sapphire Rapids CPU.
Intel Innovation 2021: Astera Labs, Broadcom, Intel & Samsung PCI Express® 5.0 Demo
Astera Labs joined Broadcom, Intel, and Samsung at Intel Innovation 2021 to demonstrate seamless end-to-end PCI Express® (PCIe®) 5.0 interoperation at 32GT/s.
Aries Smart Retimer for PCIe 5.0 and CXL
Learn about Aries Smart Retimers enabling PCIe® 5.0 system level testing on Sapphire Rapids-based platforms using PCIe 4.0 endpoints and sub 10ns latency for CXL™ applications.
Ready to find out more?
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