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Connectivity Enriches Our Connections
See how our semiconductor-based connectivity solutions are transforming the future of AI.
Introducing Aries 6 Smart DSP Retimers: First Look Demo
Get your first look at a live demonstration of how the third generation Aries Smart DSP Retimers can extend robust, low-power PCIe 6.x/CXL 3.x reach in complex AI topologies.
Aries PCIe®/CXL® Smart Cable Modules™: DesignCon Demo
At DesignCon, we showcased our new Aries PCIe®/CXL® Smart Cable Modules (SCMs) that enable multi-rack GPU clustering for AI with an industry-leading 7-meter reach over flexible copper cables.
Aries PCIe®/CXL® Smart Cable Modules™: First Look Demo
Get your first look at an end-to-end demonstration of our Aries PCIe/CXL Smart Cable Modules (SCMs) that enable multi-rack GPU clustering for AI with an industry-first 7 meters reach over flexible copper cables.
Interop Bulletin: Astera Labs Completes Interop Testing with 5th Gen Intel Xeon Scalable Processors
We’ve collaborated with Intel to offer our portfolio of PCIe® and CXL® solutions to unleash the full potential of 5th Gen Intel Xeon Scalable processors. We have completed rigorous interoperability testing in our Cloud-Scale Interop Lab to enable hyperscalers and OEMs to mitigate design risks, accelerate time-to-market, and deploy Intel-based platforms with confidence at cloud-scale.
Unprecedented Scale for Cloud and AI Infrastructure at OCP Global Summit 2023
At OCP Global Summit, we showcased how our PCIe, CXL, and Ethernet connectivity solutions deliver unprecedented reach, unprecedented memory capacity and bandwidth, and unprecedented flexibility.
Leo CXL Smart Memory Controllers Break Through the Memory Wall
At Intel Innovation this year, we showcased how Astera Labs is the first to break through the memory wall! Our Leo CXL Smart Memory Controllers are the industry’s highest performance controllers on the market, and combined with 5th Gen Intel Xeon Scalable Processors, Leo enables unprecedented performance by increasing memory bandwidth and capacity by 50%.
Interop Bulletin 2: Interop Testing with Leo CXL Smart Memory Controllers and DDR5-5600 RDIMMs
In our Interop Bulletin, we demonstrated interoperability between our Leo CXL Memory Connectivity Platform and DDR5-5600 RDIMMs from Micron, Samsung, and SK hynix.
Demo: Accelerating Database Performance with Leo CXL Smart Memory Controllers
This video highlights our joint demo with Supermicro and MemVerge at Flash Memory Summit. We showcased a high-performance OLTP (Online Transaction Processing) solution with CXL-attached memory. This collaboration has proven to increase transaction throughput, reduce infrastructure costs and improve user experience for popular services used every day, such as product delivery services, online bookings, online payments, and order tracking and monitoring.
Unlock Peak Performance for Storage Applications with Aries PCIe/CXL Smart DSP Retimers
At Flash Memory Summit 2023, we demonstrated how to unlock peak performance in a storage application with our Aries PCIe/CXL Smart Retimers and the storage-optimized X13 BigTwin server from Supermicro.
Industry’s First CXL 2.0 RAS Capabilities Demo
At Flash Memory Summit 2023, we demonstrated the CXL 2.0 RAS capabilities of our Leo Memory Connectivity Platform.
Astera Labs at TSMC China Technology Symposium – June 2023 (Chinese)
Astera Labs’ Head of Sales and Operations for Asia, Campbell Kan, shares details on our partnership with TSMC. We recently had the opportunity to demonstrate our Aries Smart Retimers and Leo Memory Connectivity Platform – solutions optimized to enable compute-intensive generative AI – at TSMC’s China Technology Symposium.
Testing Aries Smart Retimers and 4th Gen AMD EPYC™ Processors
In this video we demonstrate how our Aries Smart PCIe Retimer with 4th Gen AMD EPYC™ Processor unlocks the potential of multi-accelerator GPU servers, powering popular AI services.
Rack-Scale Demo of Taurus Ethernet Smart Cable Modules
Check out this video demo of our Taurus Ethernet Smart Cable Modules™. Learn about the benefits of Active Electrical Cables and how Taurus enables up to 100G/lane PAM4 for Switch-to-Server and Switch-to-Switch interconnect, at rack scale.
Demo: CXL Memory Pooling
The industry’s first CXL memory pooling solution to reduce memory stranding, optimize memory utilization and reduce TCO for cloud servers from Astera Labs.
Extend reach with Aries Smart Retimers
Learn how our Aries Smart Retimers extend reach and overcome signal integrity for complex topologies with advanced diagnostics features for PCIe 4.0/ 5.0 and CXL.
Interop Testing with CXL 1.1 Host CPU’s and Popular DDR5 Memory Module
After establishing the foundation of our rigorous testing, we worked with our customers to determine the most popular memory configurations for their systems and applications, to which we’ve included in our initial interop reports. We include 64GB DDR5-4800 RDIMMs from Micron, Samsung, and SK Hynix, each of which are tested with CXL 1.1-capable CPUs from AMD and Intel.
CXL from Promise to Reality with Real Silicon on Customer Platforms
Astera Labs is developing purpose-built data and memory connectivity solutions that remove performance bottlenecks throughout the data center. Our silicon, software, and systems-level solutions based on CXL, PCIe and Ethernet technologies are helping our customers realize the vision of Artificial Intelligence and Machine Learning in the Cloud.
How We Test: Leo Memory Connectivity Platform
Learn how our comprehensive interoperability testing reduces design challenges, so you can accelerate time-to-market, streamline development efforts and reduce costs for designing and deploying heterogeneous infrastructure with CXL technology.
Astera Labs Advances CXL Technology Ecosystem
Astera Labs and AMD collaborate to help realize the vision of AI and Machine Learning in the Cloud with 4th Gen AMD EPYC™ Processors
Leo Memory Connectivity Platform: First look demo
Get your first look and an end-to-end demonstration of Astera Labs Leo Memory Connectivity Platform for CXL™ 1.1 and 2.0, the industry’s first purpose-built solution to support memory expansion, pooling and sharing.
Unlock the full potential of CXL with Leo Memory Connectivity Platform
Learn about Astera Labs Leo Memory Connectivity Platform, the industry’s first purpose-built solution to unlock the full potential of data-centric systems based on Compute Express Link™ technology.
Intel Vision 2022
Check out this demo video from Intel Vision featuring our Aries PCIe® Smart Retimers enabling robust PCIe 5.0 connectivity with KIOXIA America, Inc. SSDs and Intel Corporation’s Sapphire Rapids CPU.
Deploy Robust PCIe® 5.0 Connectivity with Aries Smart Retimers
See our Aries Smart Retimers in action via two interoperability demonstrations with key industry partners’ PCIe® 5.0 root complex and endpoints.
Astera Labs & Intel Capital
Astera Labs Co-Founders Sanjay Gajendra, Jitendra Mohan, and Casey Morrison highlight the company’s enduring partnership with Intel Capital.
Taurus Smart Cable Module™ 400GbE PAM4 Connectivity Demonstration
See a Taurus Smart Cable Module™ enabled 400GbE PAM4 Smart Electrical Cable in action with a demonstration of an end-to-end 400GbE link up passing error-free traffic as well as real-time link diagnostics.
Intel Innovation 2021: Astera Labs, Broadcom, Intel & Samsung PCI Express® 5.0 Demo
Astera Labs joined Broadcom, Intel, and Samsung at Intel Innovation 2021 to demonstrate seamless end-to-end PCI Express® (PCIe®) 5.0 interoperation at 32GT/s.
Aries CXL™ Smart Retimer Demo: CXL Ecosystem Interop with Intel and Synopsys
Industry’s first demonstration of a fully formed CXL™ link between an Intel root complex, an Aries CXL Smart Retimer and Synopsys end point IP.
Taurus Smart Cable Module™: First Look at Purpose-Built 100GbE/Lane Connectivity
Get your first look at Taurus Smart Cable Modules™ – the only “active” plus “smart” hyperscale connectivity solution that’s ready to support the jump to 100G/Lane Ethernet when you are.
Taurus Smart Cable Module™: “Active” + “Smart” 100G/Lane Ethernet Connectivity
Learn how Taurus Smart Cable Modules™ enable the hyperscale industry’s transition to 25G, 50G and 100G/Lane Ethernet for cost effective 200GbE, 400GbE and 800GbE interconnects.
Introduction to Compute Express Link™ (CXL™) Technology
Learn how CXL™ technology enables data centers to achieve higher performance through increased memory capacity and bandwidth at lower latencies.
CXL 2.0™ Overview
CXL™ 2.0 moves beyond a single node to provide breakthrough performance at larger scale and introduces single level switching, memory pooling and enhanced security mechanisms.
Aries Smart Retimer for PCIe 5.0 and CXL
Learn about Aries Smart Retimers enabling PCIe® 5.0 system level testing on Sapphire Rapids-based platforms using PCIe 4.0 endpoints and sub 10ns latency for CXL™ applications.
Astera Labs: Stellar by Design
Let’s talk about Astera Labs. Who we are, where we’re going and what we’re doing.
Complex PCIe® Topologies with Switches, SRIS Clocking & Aries Smart Retimers
Learn about PCIe® switches and why certain complex system topologies involving switches need retimers to achieve optimal link performance.
Why We Test
Interoperability testing of PCIe® retimers is critical for HPC and cloud applications to support new compute-intensive workloads – such as Artificial Intelligence (AI) and Machine Learning (ML).
Interop Testing for Enterprise NVMe SSD Deployments
Learn about some specific interop test cases required by our enterprise NVMe SSD customers.
Interop Testing for Popular Endpoints
Overview of some enterprise PCIe® 4.0 endpoints featured in the Aries PCIe Smart Retimer Interop Report and use cases that require unique test setups for specific device functionalities.
How We Test
Each Aries Smart Retimer device is put through our exhaustive testing regime that uses the latest PCIe® 4.0 systems.
Signal Integrity Challenges for PCIe® 5.0 OCP Topologies
Astera Labs explains the signal integrity challenges of PCIe® 5.0 and the corresponding OCP system design challenges, where the right balance must be found between PCB materials, connector types, and the use of signal conditioning devices for practical compute topologies.
Flywheels of Innovation
Our partnership with AWS, Intel and Six Nines is revolutionizing semiconductor development in the cloud.
Connectivity Solutions for Computation-Intensive Workloads
Astera Labs CEO discusses our collaboration with Intel Capital to accelerate deployment of connectivity solutions for computation-intensive workloads.
PCIe® 5.0 and PCIe 6.0 Overview
PCI-SIG® shares an overview of PCI Express® (PCIe®) 5.0 and PCIe 6.0 specifications, including expected performance boosts, key features, and target applications.
