News & Articles
October 22, 2019
"Rather than taking an incremental approach to adding bandwidth capabilities, we took a ground-up approach to optimize our Retimers for workload-optimized platforms that demand low latency and cloud-scale management capabilities. Built in the cloud, for the cloud, with our Aries portfolio we are pioneering PCIe Smart Retimer solutions for the industry."
October 21, 2019
“We would never have been able to do the same number of simulations and checks in a traditional environment… In the cloud we could fire 1,000 or 1,500 cores and run verification jobs in parallel with physical design to test the heck out of our chip in a relatively short time. It meant we were able to move very quickly while also ensuring a quality product.”
Astera Labs Verifies Its System-Aware PCI Express 5.0 Smart Retimer Using Avery Design Systems PCIe 5.0 Verification IP
June 18, 2019
"Astera Labs successfully utilized Avery's Peripheral Component Interconnect PCI Express® (PCIe®) 5.0 Verification IP and services to verify its breakthrough system-aware PCIe 5.0 Smart Retimer."
Synopsys Design and Verification Solutions Enable Astera Labs to Develop Industry's First PCIe 5.0 Retimer SoC
May 30, 2019
"The collaboration represents two game-changing industry milestones: the first large-scale design fully implemented and verified from start to finish on a third-party public cloud, and the industry's first PCIe 5.0 retimer for heterogenous compute and workload-optimized servers."
May 29, 2019
"Heterogeneous computing and workload-optimized platforms are redefining the connectivity backbone in the next generation of servers. Specialized semiconductors will help enable this high-speed connectivity backbone and accelerate technology adoption."
May 23, 2019
"With the benefits of high throughput, low latency, and the ability to carry alternate protocols, PCIe 5.0 is poised to unify server communication and form the connectivity backbone in modular servers for years to come."
May 21, 2019
"With the deployment of more servers, each one having more compute density, the challenges associated with moving data between processor, networking and storage nodes cost-effectively are exploding; and signal integrity (SI) will be the primary pain point for these densely-packed systems."
May 29, 2019
"The new specification increases performance in the high-performance markets including artificial intelligence, machine learning, gaming, visual computing, storage and networking."
March 11, 2019
"[CXL] will use current PCIe 5.0 standards for physical connectivity and electrical standards, providing protocols for I/O and memory with coherency interfaces. The focus of CXL is to help accelerate AI, machine learning, media services, HPC, and cloud applications."
February 14, 2019
"While the adoption of 32 GT/s PCIe 5.0 technology is on an accelerated pace, SoC designers must understand and handle a few design challenges as they make the shift. 32 GT/s designs have challenging NRZ channels that are extremely lossy and bumpy with many discontinuities, with insertion loss reaching 36 dB and beyond."
January, 17, 2019
"PCI-SIG expects [Gen-4 and Gen-5] to co-exist in the market for some time, with PCIe 5.0 used primarily for high-performance devices that crave the ultimate in throughput, like GPUs for AI workloads, and networking applications....less-intense applications, like desktop PCs, are fine with the PCIe 4.0 interface."