Senior Design Verification Engineer

Multiple Positions


Astera Labs, Inc., 2901 Tasman Drive, Suite 204, Santa Clara CA 95054.


The Senior Design Verification Engineer will be responsible for the following job duties:

  • Defining a comprehensive design verification methodology for a complex SoC which can ensure that the product
    will comply to a variety of industry standards (PCIe, I2C, Ethernet,
    etc.) and meet numerous customer-specific requirements;
  • Developing an SoC verification environment based on Universal Verification Methodology (UVM) principles to
    enable functional verification and formal verification of SoC designs;
  • Creating, reviewing, and implementing test plans, test cases, and test procedures to ensure complete functional
    and non-functional test coverage for high-speed communication protocols and associated verification IPs (VIPs);
  • Running tests and regression simulations, reviewing results, and identifying root cause for any/all failing cases
    using Synopsys VCS simulator;
  • Implementing necessary changes in the register transfer language (RTL) design based on simulation results and
    root cause analysis.

This position requires a Bachelor’s or foreign equivalent in EE; CE; or clsly related field and five years of progressive professional
experience as a Dsgn/Verf Egr; Staff Egr or closely related occupation.

Must have professional experience with:

  • Peripheral Component Interconnect Express (PCIE);
  • Ethernet – Media Access Control and Physical Coding Sublayer;
  • IP and Block level verification;
  • System On Chip (SoC) Verification;
  • System Verilog and Universal Verification Methodology (UVM).


Kushagra Saxena [email protected]

Key Job Details



Bachelor’s or foreign equivalent in EE; CE; or closely related field and Five (5) year progressive professional experience

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