Senior Design Verification Engineer

Multiple Positions

Location:

Astera Labs, Inc., 2901 Tasman Drive, Suite 204, Santa Clara CA 95054.

Duties:

With a high degree of independent decision-making capability and minimum supervision, the Senior Design Verification Engineer will be responsible for architecting System on a Chip (SoC) design verification and overseeing chip verification environment, tests and implementation and defining protocol performance for Astera Labs’ proprietary semiconductor connectivity technology. Duties include:

  • Defining a comprehensive design verification methodology for a complex SoC which can ensure that the product will comply to a variety of industry standards (PCIe, I2C, Ethernet, etc.) and meet numerous customer-specific requirements;
  • Developing an SoC verification environment based on Universal Verification Methodology (UVM) principles to enable functional verification and formal verification of SoC designs;
  • Creating, reviewing, and implementing test plans, test cases, and test procedures to ensure complete functional and non-functional test coverage for high-speed communication protocols and associated verification IPs (VIPs);
  • Running tests and regression simulations, reviewing results, and identifying root cause for any/all failing cases using Synopsys VCS simulator;

Education:

Bachelor’s or foreign equivalent in EE; CE; or clsly related.

Experience:

Five (5) year progressive professional experience as a Software/ Product/Staff/ Design/ASIC /Verification Engineer, or closely related occupation.

Alternative Education and Experience

Alt. Education: In the alternative, Master’s Degree or foreign equivalent in EE; CE; or closely related field

Alt. Experience: Three (3) years of experience Software/ Product/Staff/ Design/ASIC /Verification Engineer, or closely related occupation.

Skills Required:

Must have experience with:

  • Simulation tools like: VCS or IES or Questa;
  • C++ or C;
  • Python or Perl or Scripting language;
  • PCIE or Ethernet or DDR;
  • System Verilog or Verilog;
  • Universal Verification Methodology (UVM);
  • Verification plan definition and execution or Verification process and flows.

Contact:

Kushagra Saxena, [email protected]

Key Job Details

Category:

Locations:

Experience:
Bachelor’s or foreign equivalent in EE; CE; or closely related field and Five (5) year progressive professional experience or Masters or foreign equivalent in EE, CE, or closely related field and 3 years of experience.

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