Senior Physical Design Engineer

We are looking for senior Physical Design Engineers with experience in SOC Physical design from netlist synthesis to tape-out.

Astera Labs Inc., a leader in purpose-built connectivity solutions for data-centric systems, is seeking Senior Physical Design Engineers for their Santa Clara (California) Design Center. Partnering with leading processor vendors, cloud service providers, seasoned investors and world-class manufacturing companies, Astera Labs is helping data-centric system designers remove performance bottlenecks in compute-intensive workloads such as Artificial Intelligence and Machine Learning. For more information about Astera Labs, see

We are looking for Senior Physical Design Engineers with experience in SOC Physical design from netlist synthesis to tape-out. The candidate is expected to take an RTL through synthesis, floorplanning, pad selection, DFT all the way to tapeout of GDSII. The candidate will deal with all aspects of Physical design including DFT, floor planning and routing, physical design convergence. The candidate is expected to have worked on bleeding edge technologies and ASIC designs in the networking, compute or storage.

Basic qualifications

  • Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred.
  • ≥10 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
  • Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
  • Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!

Required experience

  • Hands-on and thorough knowledge of synthesis, place and route, timing, extraction and other backend tools and methodologies for technologies 16nm or less.
  • Proven expertise in synthesis, timing closure and formal verification (equivalence) at the block and full- chip level.
  • Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production.
  • Experience with Cadence and/or Synopsys physical design tools/flows.
  • Familiarity and working knowledge of System Verilog/Verilog.
  • Experience with DFT tools and techniques.
  • Experience in working with IP vendors for both RTL and hard-mac blocks.
  • Good scripting skills in python or Perl

Preferred experience

  • Good knowledge of design for test (DFT), stuck-at and transition scan test insertion.
  • Familiarity with DFT test coverage and debug.
  • Familiarity with ECO methodologies and tools.

Key Job Details



MSEE/BSEE; 5+ years

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