NCG: Design or Verification Engineer

We are looking for new college graduates (Design and/or Verification) to join our ASIC team working on the forefront of high-performance compute and networking standards in advanced CMOS process nodes.

Astera Labs Inc., a leader in purpose-built connectivity solutions for data-centric systems, is seeking new college graduates in ASIC Design and Verification for their Santa Clara (California) Design Center. Partnering with leading processor vendors, cloud service providers, seasoned investors and world-class manufacturing companies, Astera Labs is helping data-centric system designers remove performance bottlenecks in compute-intensive workloads such as Artificial Intelligence and Machine Learning. Astera Labs is a born-in-the-cloud company, pioneering 100% SoC design and tapeout on AWS cloud. For more information about Astera Labs, see www.AsteraLabs.com.

Job Description:
We are looking for new college graduates (Design and/or Verification) to join our ASIC team working on the forefront of high-performance compute and networking standards in advanced CMOS process nodes. The ideal candidate will have an impeccable hardware engineering background with an emphasis on VLSI and/or computer architecture. We are looking for experience in design, verification, and validation of real-world systems. Exposure to high-speed interfaces PCIE, DDR, HBM, Serdes technologies would be great to have. Above all, curiosity and ability to learn is a must. In this position you will be responsible for design and/or verification of blocks using leading edge methodology and tools.

Basic qualifications:
• Pursuing MS in EE/CS or related fields.
• Minimum GPA: 3.5
• Hardware engineering background with an emphasis in VLSI or Computer Architecture.
• Exposure to Digital design or verification, VLSI design and circuits, Computer Architecture.
• Authorized to work in the US and start immediately.

Required experience:
• Hands-on and knowledge of RTL design languages and tools including Verilog, System Verilog.
• Familiarity with verification methodologies like UVM, functional coverage, assertions.
• Familiarity with any of the scripting languages Python, Perl etc and hands-on experience in C/C++.

Preferred experience:
• Real-world design and/or verification in Verilog/System Verilog.
• Knowledge of high-speed interfaces like PCIe, DDR, HBM, Serdes.
• Familiarity with Synopsys EDA tools.

Key Job Details

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Experience:
BSEE/MSEE

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