Astera Labs Inc., a leader in purpose-built connectivity solutions for data-centric systems, is seeking a Senior/Principal Firmware Engineer in Santa Clara, CA with experience implementing firmware for hardware-software interfaces on Systems on a Chip (SoCs) and microcontroller subsystems utilizing high-speed communications protocols such as PCI-Express (Gen-3 and above), DDR, Ethernet, NVMe, or similar interfaces.
The mission of this role is to validate all aspects of the memory subsystems on the ASIC and systems. This would include electrical validation of memory interfaces like DDR5 and validation of vendor memories for inter-operability. The ideal candidate must have solid hands-on experience in enterprise or cloud grade memory subsystems with strong testing knowledge. The candidate would ensure robust operation of memory technologies across all the Astera products.
- Strong academic and technical background in electrical engineering. At a minimum, a Bachelor’s in EE or Computer Science is required, and a Master’s is preferred.
- Minimum 5 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
- Minimum 2 years of experience specifically in high speed memory validation and SOC IP electrical characterization.
- Experience with firmware based operations of high speed memory sub-systems, configurations of DRAM based memories.
- Experience working with logic designers and board designers to validate and verify HW-SW interfaces on complex SoCs.
- Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer meetings in advance, and to work with minimal guidance and supervision.
- Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
- Authorized to work in the US and start immediately.
- Experience defining validation plans for functional, signal and power integrity work HW and ASIC teams to debug complex memory issues.
- Experience in system testing, characterization and compliance, margin analysis and optimization.
- Experience working with memory vendors to identify issues, working with SOC to improve memory calibration and tuning sequences.
- Experience developing automation scripts and test tools for execution efficiency, repeatability and reporting.
- Familiarity with memory standards and compliance testing.
- High level of proficiency in Python for automating pre-processors/post-processors and QC.
- Comfortable using high speed oscilloscopes, logical analysers, memory interposers.
- Extensive experience with memory debug techniques and methodologies.
- Direct experience working on enterprise grade memory subsystem validation, diagnostics and tuning.
- Experience with DRAM memory vendors on DDR4 or DDR5.