Server Base Board
Enabling Low-Cost PCB Material for Next-Gen PCIe® 5.0 Systems
The rapid innovation in specialized workloads – like artificial intelligence and machine learning – demand high-bandwidth, low-latency interconnects between processors, workload accelerators, and storage nodes. Heterogeneous computing and modular server designs are redefining the connectivity backbone in the next generation of servers.
Specialized semiconductors will help enable this connectivity backbone, and system designers expect plug-and-play interoperability to accelerate technology adoption.
RT = Retimer
Requirements & Challenges
- Signal loss at PCIe® 5.0 speed (32 GT/s) can be too high for farthest CEM slots (>5 inches from CPU)
- PCB material upgrade is prohibitively expensive and will not solve reach problem for 9+ inch slots
- Dense Base Board design requires Retimer solution with smallest total footprint
Aries Retimer Benefits
- Supports reach extension >36 dB on both Tx & Rx with best-in-class SerDes
- Minimizes total solution size with integrated decoupling and AC caps
- Saves BoM cost > save system cost
- Up to 16 Lanes with Flexible Link Bifurcation Including 1x16, 2x8, 4x4, 8x2, and others
- Deep diagnostic features provided in BMC-qualified SDK
Products
Product | Documents | Description | Max PCIe Gen | PCIe Lanes | Ordering |
Astera Labs PCIe® 4.0, PCIe 5.0, and CXL™ x16 and x8 Low-Latency Smart Retimers | PCIe 5.0 | x 8 |