Non-Transparent Bridge
Enabling Low-Latency CPU-to-CPU Interconnects
RT = Retimer
Requirements & Challenges
- CPUs on different server nodes interconnect via back plane, and passing through multiple connectors at PCIe® 4.0 and PCIe 5.0 speeds causes more reflections and insertion loss
- Low-latency interconnect required between CPUs makes PCIe switches undesirable
- Each base board has its own clocking domain, so the NTB must support separate reference clocks
Aries Retimer Benefits
- Retimers can be cascaded for extra-long back plane PCBs, or cabled NTB applications
- Protocol-transparent low-latency modes enable < 10 ns added latency between CPUs
- Supports separate reference clock to accommodate PCIe interconnect without needing to send REFCLK across the midplane
Products
Product | Documents | Description | Max PCIe Gen | PCIe Lanes | Ordering |
Astera Labs PCIe® 4.0, PCIe 5.0, and CXL™ x16 and x8 Low-Latency Smart Retimers | PCIe 5.0 | x 8 |