As a valued customer, we cordially invite you to attend our 2nd annual Supernova event with the Astera Labs executive team. We will provide you with an update on our company, a sneak preview of our new products and roadmaps as well as live demonstrations of our newest CXL™, PCIe® and Ethernet connectivity solutions. We also look forward to hearing from you on opportunities to better serve you as a valued partner.
Dates: October 10 – 14, 2022
Location: Astera Labs HQ
RSVP: Please respond to the email you received
Agenda
Topic | Speaker(s) | Discussion |
---|---|---|
Company Update | Sanjay Gajendra
Patrick Henderson |
|
Product Roadmap Update | Sanjay Charagulla
Richard Ward |
|
Engagement Review | Astera sales account team |
|
Demos
After the sessions, we invite you to tour our lab and experience live demos featuring the latest Astera connectivity products.
CXL 1.1 Memory Expansion
Leo Memory Connectivity Platform overcomes processor memory bottlenecks and capacity limitations to increase performance and reduce TCO for applications ranging from AI, machine learning and in-memory databases. In this demo, we will showcase CXL 1.1 memory expansion with Leo running real workloads and performance benchmarks on Intel Sapphire Rapids and AMD Genoa CPUs.
CXL 1.1 Memory Pooling
Leo Memory Connectivity Platform supports memory pooling to reduce memory stranding, optimize memory utilization and reduce TCO for cloud servers. While CXL 3.0 specification has added support for dynamic memory pooling, this demo will showcase how memory pooling can be deployed today with Leo and CXL 1.1 CPUs from Intel and AMD.
Expand Memory & Extend Reach with CXL
Increasing server performance and developing heterogenous solutions for memory expansion and pooling requires complex system topologies that introduce signal integrity challenges. In this demo, we will showcase how Astera Labs is leading the way for cloud-scale CXL deployment by extending signal reach with Aries Smart Retimers and expanding memory with Leo Memory Connectivity Platform.
Extend Signal Reach with PCIe 5.0
Heterogeneous compute architectures enable data-intensive workloads such as AI and machine learning but introduce signal integrity challenges as transitioning from PCIe 4.0 to PCIe 5.0. Aries Smart Retimers extend signal reach and enable complex system topologies in a variety of data center use cases.
Deploy Robust PCIe 5.0 Connectivity with Aries Smart Retimers
Astera Labs is driving the PCIe ecosystem readiness by early and successful interop with all major PCIe 5.0/4.0 Root complex and endpoints (CPU, SSD, FPGA, Switches, GPU, NIC) in the market. In the Aries Cloud-Scale Interop Lab, we've exercised the PCIe links with thousands of iterations of loop tests, ensuring our Aries PCIe Smart Retimers are robust to deploy into customers’ systems.
100G per lane Ethernet Connectivity
Taurus Smart Cable Modules help overcome reach, signal integrity and bandwidth utilization issues for 25G/50G/100G per lane Ethernet connectivity for Switch-to-Switch and Switch-to-Server applications. Demonstrating EM200QDX, EM200QX and EM400QX Smart Ethernet Modules.
Location
Join us at the Astera Labs headquarters:
2901 Tasman Dr., Suite 204
Santa Clara, CA 95054