Asteral
  • Applications
  • Products & Services
    • Aries Smart Retimers
    • Systems
    • Services
    • Cloud-Scale Interop Lab
  • Resources
  • News
    • Astera Labs News
    • Industry News
  • Careers
  • About
    • About Us
    • Contact Us
    • Careers

Simulating with Retimers for PCIe 5.0

Home > General > Simulating with Retimers for PCIe 5.0

Simulating with Retimers for PCIe 5.0

March 16, 2020 by Casey Morrison

The design solution space for high-speed serial links is becoming increasingly complex as data rates climb, channel topologies become more diverse, and tuning parameters for active components multiply. PCI Express 5.0, at 32 GT/s, is a particularly relevant example of an application whose design solution space can be a daunting problem to tackle given the low-cost nature of its end-equipment. This paper is intended to help system designers navigate through these design challenges by providing a how-to guide for defining, executing, and analyzing system-level simulations including PCIe 5.0 Root Complex (RC), Retimer, and End Point (EP).

Link to Paper

Link to Slides

1,131
6+

Filed Under: General Tagged With: DesignCon, PCIe, PCIe 5.0, Retimers

Search

Categories

  • Cloud-Scale Interop Lab
  • General

Archives

  • December 2020
  • June 2020
  • May 2020
  • April 2020
  • March 2020
  • October 2019
  • June 2019
  • January 2019
Asteral

Follow Us

Copyright © 2020 Astera Labs, Inc. All rights reserved I Site Map I Privacy Policy I Terms and Use